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Hello Hao-san.
Thank you for your support.
I have found the following application notes.
http://www.tij.co.jp/jp/lit/an/scba004d/scba004d.pdf
The slow input value for CMOS & BiCMOS is specified for P3.
If SN75C1168 has no provision for slow input,
Based on the value of 5 μs to 10 μs, should I design in less time?
Best Regars.
Fukazawa
Fukazawa-san,
Thanks for the information. I understand your concern now. My two cents why it's not an issue: 1) SN75C1168 has 2 channels. Therefore if the throughput current happened, it would not generate the heat problem as bad as a 10 bit or 16 bit device; 2) SN75C1168 works with Mbps data rate, which means rise/fall time of the input data can be around 10s of ns that is far from the slow input region.
Please let me know if you have more questions.
Regards,
Hao