RTOS/SN65DSI86: SN65DSI86 support pannel question

Hugo

What is the frame rate and BPP of the panel?

I sent you a friendship request, please accept it so I can send you the SN65DSI86 register calculation spreadsheet, you can use it to see if DSI86 is able to support this particular panel.

Thanks
David

Hi David ,
We have two options of the panel:
1.Sharp panel : WQHD(2560x1440) , BPP 24 , eDP Transfer rate : 2.7Gbps / 4 lane
2.AUO panel : FullHD(1920x1080) ,BPP16 , 2 Lane eDP 1.2

Want to make sure is that possible to only use MIPI 4 lanes to control teh Panel Option 1
For Panel Option 2 :
I think that is Ok , MIPI 4 lanes can support up to FullHD video stream , right ?

Thanks
Ben

Ben

Please refer to this app note: www.ti.com/.../slla425.pdf section 3 for the calculation.

DP_Datarate_Supports needs to be greater or equal to (DP_Total_Bit_Rate/DP lanes)

Thanks
David

Hi David ,
For AUO panel spec :
HD(1920x1080) , 18bpp , 2 Lane eDP / data rate 2.7Gbps , (pixel clock) 152.6 MHZ
assume that host GPU 650 Mhz.

Can you help to confirm my calculation is correct ?
1. Stream Bit Rate = PixelClock x bpp
=> Stream Bit Rate = 18 x 152.6MHZ = 2.7468 Gbps
2. eDPTotalBitRate = # _of_eDP_Lanes x DataRate x 0.6 ( => I change to 0.6 due to 6b/10b encoding for 18bpp(RGB666) ?)
=> eDPTotalBitRate = 2 x 2.7Gbps x 0.6 = 3.24 Gbps
3. eDP_Datarate_Supportes >= (eDP_Total_Bit_rate/eDP_Lanes)
=> (eDP_Datarate_Supportes) 2.7Gbps >= 1.62 (Minimum number of lanes : 2 lane is OK)
4. Min_number_of_DSI_Lanes = Stream_Bit_Rate / (2 x max_DSI_Clock) (using REFClk = 19.2Mhz)'
=>Min_number_of_DSI_Lanes = 2.7468Gbps / (2 x 500Mhz) = 2.7468 lane (at least using 4 lanes)
5. Min_Required_DSI_Clock_Frequency = Stream_Bit_Rate/Min_number_DSI_Lanes x 2)
=> Min_Required_DSI_Clock_Frequency = 2.7468Gbps / 4 x 2 = 343.4 Mhz ( so I need to config DSI clock greater then 343.4Mhz )

So host using MIPI DSI 4 lanes to eDP to control AUO panel is OK , right ?

Thanks
Ben.

Hi David sir

We need support these panel as below.

  1. sharp (2560x1440 WQHD)

  2. auo (1080 x 1920 fullHD)

  3. samsung (1366x678)

 

Could you help to provide the setting regarding in datasheet as attachment?

Thanks for your great support.

 

 

 

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/3_5F00_panels.7z

Hugo

I send you the programming spreadsheet, you can use it to program the DSI86 register.

Thanks
David

Hi David sir

We hvae two questions about EVM seeting as below.

1. Can we use DP to HDMI convertor at DP port (J9) and connected with HDMI monitor display ?
2. If Q1 answer is yes, what different set eDP mode at SN65DSI86? When need process DSI sequnce?


Thanks for your great support.

Hugo

You need to use an active DP to HDMI converter for this application. But the sequence is still the same for SN65DSI86 since the conversion is handled by the active adapter.

Thanks
David

Hi David ,

1)As I know the panel DSI init sequence is generated by datasheet , and need calculate by programing spreasheet , but if I using a any exernal panel , How do i know to fill the colume of EDID Information in programming dataspreed.

2) Another question for the my exercise on EVM , Does SN65DSI86 support on Qualcom platfrom MSM8953 , can I get a referenece porting driver from TI side ? (before our target is going on WOS platform)

By the way , if possible can we discuss by mail ? (Hugo can help involved) , i'm doing some exercise need support , would be convenient describe detail with figure of picture or some attached file as reference.

Thank you!

Sorry, correct it , Q1 is based on situation :(DP-> Dp to HDMI converter -> external display)
1)As I know the panel DSI init sequence is generated and referring from panel datasheet and calculate by programming spreadsheet , but if I using a any external display device(a HDMI input) , How do i know to fill the colunm of "EDID Information" in programming spreadspreed.

Thanks

Wenyu

You can read the EDID info through DSI86, DSI86 supports both direct and indirect method of reading EDID.

1. Using the direct method, SW needs to program I2C_ADDR_CLAIMx registers and enable them. Once this is done, any
I2C transaction that targets the I2C_ADDR_CLAIMx address will be translated into a I2C-Over-AUX transaction. In order
to use the direct method, the I2C master must support clock stretching.
2. Using the indirect method, SW needs to use Native and I2C-Over-Aux registers. When using the indirect method, the
maximum read size allowed is 16 bytes. This means reading the EDID must be broken into 16-byte chunks.

Please see DSI86 datasheet for the example code of indirect method.

For Qualcomm platform, I do not have any porting driver.

Thanks
David

Hi David ,

Our option panel is :
Sharp panel: WQHD(2560x1440)
Attached panel data sheet for referecne :7318.Sharp_LQ125T1JX03C+T300chi+WQHD-(OK).pdf

[Question1]: Can you help to review my calculation is correct please ?
(1)Stream bit rate = PixelClock x bpp
241.5 Mhz x 24 = 5.796 Gbps
(2)eDP Total bit rate :
公式: eDPTotalBitRate = #_of_eDP_Lances x DataRate x 0.8
 eDPTotalBitRate = 4 x 2.7Gbps x 0.8 = 8.64Gbps
(3)Minimum Number of eDP lances.
公式: eDP_Datarate_support >= (eDP_Total_Bit_Rate/eDP_Lanes)
 (eDP_Datarate_support)2.7Gbps >= 2.16Gbps (minumun number of eDP lanes 4 lanes is OK )
(4) Minimum DSI Lanes and DSI Clock Frequency
公式: Min_number_of_DSI_Lanes = Stream_Bit_Rate / ( 2 x max_DSI_Clock
 Min_number_of_DSI_Lanes = 5.796 Gbps / (2 x 680Mhz) => 4.26 => at lesast 8 lanes
(5) Min_Reguired_DSI_Clock_Frequency = Stream_Bit_Rate / Min_Number_DSI_Lanes x 2)
 Min_Reguired_DSI_Clock_Frequency = 5.796/ (8x2) = 362.25Mhz

[Question2]I have filled panel's & EDID information in attached spreadsheet, can you help to review and point me if wrong ? 
   https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/Sharp_5F00_LQ125_5F00_PANEL_5F00_VIDEOREGISTER_5F00_CALC.7z
[Quesiont3] I' not sure the items in Main_Inputs_page :
- HSync_Polarity : NEGATIVE is correct ?
- Vsync_Polarity : NEGATIVE iss correct ?
- Max DP datarate for DP Panel : HBR is correct ? (2.7Gbps)
- How to used the "LEFTRIGHT MODE ONLY" and how to fill it ?
- How to used the "Color Bar column" and how to fill it ?
- How to check sharp panel is ASSR or noASSR

Thank you.!

Ben

2.7G is HBR.

If you don't plan to use left/right mode, you can ignore that portion of table.

I would recommend to use the color bar first, color bar is generated internally from DSI86. So by using the color bar, you can completely isolate the DSI interface first.

Most panel does not support ASSR (noASSR).

Thanks
David

Hi David , 

Our schedule is tight in these days , we need got correct DCS command sequence confirm by TI.  Can you provided QC dsc command sequence to us ?

I have attached  the calculating sheet & spec for your reference.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/SharpPAnelCaulate.7z

Hi David  ,

I have  AUO panel (1920 x 1080 , 2 edp lane , 18BPP) bringup issue , the status is 

1. Panel EDID and settings was input and sequence generated from tool as below:   

Datasheet EDID Information	Manual Inputs
Panel Vendor	AUO
Panel Model#	B125HAN01.0
Resolution	1920x1080
Pixel Clock	152.60
Horizontal Active (pixels)	1920
Horizontal Blanking (pixels)	310
Vertical Active (lines)	1080
Vertical Blanking (lines)	60
Horizontal Sync Offset or FrontPorch (pixels)	48
Horizontal Sync Pulse Width (pixels)	100
Vertical Sync Offset or FrontPorch (lines)	3
Vertical Sync Pulse Width (lines)	1
Hsync Polarity	NEGATIVE
Vsync Polarity	NEGATIVE

Category's	DP/DSI Settings
# of DP Lanes for DSI86	2
# of DP Lanes for DP Panel	2
Max DP datarate for DP Panel	HBR
# of DSI A Lanes	4
# of DSI B Lanes	0
DSI Video mode	RGB666
DSI Channel Mode	Single
Even/Odd or Left/Right	EvenOdd
REFCLK FREQ (MHz)	19.2

 

<DSIInitSequence>
23 FF 7
23 16 1
23 FF 0
23 0A 2
23 10 26
23 12 44
23 13 44
23 94 80
23 5C 1
23 0D 1
FF 2A
23 5A 4
23 93 20
23 96 0A
FF ff
23 20 80
23 21 07
23 22 0
23 23 0
23 24 38
23 25 04
23 2C 64
23 2D 00
23 30 01
23 31 00
23 34 A2
23 36 38
23 38 30
23 3A 03
23 5B 1
23 3C 16
23 5A 0C
23 5F 80
23 A0 4B
23 A1 FF
23 A2 00
23 A5 02
</DSIInitSequence>

2. Backlight is working (PWM singnal outputed normally)

3.  Color bar mode is fine(@0x3C:0x16) . we can see correct color bar  in 3 colors(RGB). 

4. We can't see the display .

5. I have attached the related data in zip , with the dump file of sn65dsi86 REG( after sending dsi initial sequence)

can you help to review above information and point out ?

Thanks

Ben.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/Auo-data.7z

Hi David,
Athother question :
If this AUO Panel(FHD 1920x1080) only using signle DSI path enough but our hardware design connected to both DSI0 & DSI1 . Should it be ok if software configure to single or dual DSI mode for this panel ?

Thanks
Ben.

Ben

If only single channel is used, it is still ok to have the hardware design connected to both DSI0 and DSI1. But software needs to configure for single DSI mode. If software configures dual DIS mode, then SN65DSI86 supports ODD/EVEN configurations and LEFT/RIGHT configurations. In the ODD/EVEN configuration, the odd pixels for each scan line are received on channel A, and the even pixels are received on channel B. In LEFT/RIGHT mode, the left portion of the line is received on channel A, and the right portion of the line is received on channel B.

Can you please set register 0x5Ah to 0x0D and see if display works? If not, can you please see if you can successfully read back the monitor EDID information?

Thanks
David

Hi David , 

It's still not work after write register 0x5AH to 0x0D , i have no idea what going on .

What's EDID infomation to readback is needed ? 

I Connect the panel to PC's external display port that can dump the EDID info via a PC Tool showed as below  and Can you please help to check what might be the problem?

EDID ( Extended Display Identification Data) Report

Vendor/Product Identification:

Monitor Name :
Monitor Serial Number :
Manufacturer Name : AUO
Product Id : 106D
Serial Number : 0
Week Of Manufacture : 0
Year Of Manufacture : 2014
EDIDVersion : V1.4
Number Of Extension Flag : 0

Display parameters:

Video Input Definition : Digital Signal
DFP1X Compatible Interface : True
Max Horizontal Image Size : 280 mm
Max Vertical Image Size : 160 mm
Max Display Size : 12.7 Inches

Power Management and Features:

Standby : Not Supported
Suspend : Not Supported
ActiveOff : Not Supported
Video Input : 0
sRGB Default ColorSpace : False
Default GTF : Not Supported
Prefered Timing Mode : True

Gamma/Color and Etablished Timings:

Display Gamma : 2.2
Red : x = 0.587 - y = 0.35
Green : x = 0.342 - y = 0.585
Blue : x = 0.154 - y = 0.115
White : x = 0.305 - y = 0.32

Etablished Timings :

Display Type : Monochrome

Standard Timing:

Preferred Detailed Timing:

Pixel Clock : 152.6 Mhz

Horizontal Active : 1920 pixels
Horizontal Blanking : 310 pixels
Horizontal Sync Offset : 48 pixels
Horizontal Sync Pulse Width : 100 pixels
Horizontal Border : 0 pixels
Horizontal Size : 276 mm

Vertical Active : 1080 lines
Vertical Blanking : 60 lines
Vertical Sync Offset : 3 lines
Vertical Sync Pulse Width : 1 lines
Vertical Border : 0 lines
Vertical Size : 155 mm

Input Type : Digital Separate
Interlaced : False
VerticalPolarity : False
HorizontalPolarity : False

Monitor Range Limit:

Maximum Vertical Frequency : 0 Hz
Minimum Vertical Frequency : 0 Hz
Maximum Horizontal Frequency : 0 KHz
Minimum Horizontal Frequency : 0 KHz
Maximum Pixel Clock : 0 MHz

Stereo Display:

Stereo Display : Normal display (no stereo)

RAW Data:

0x00 00 FF FF FF FF FF FF 00 06 AF 6D 10 00 00 00 00
0x10 00 18 01 04 95 1C 10 78 02 6B A0 96 59 57 95 27
0x20 1D 4E 52 00 00 00 01 01 01 01 01 01 01 01 01 01
0x30 01 01 01 01 01 01 9C 3B 80 36 71 38 3C 40 30 64
0x40 31 00 14 9B 10 00 00 18 00 00 00 0F 00 00 00 00
0x50 00 00 00 00 00 00 00 00 00 20 00 00 00 FE 00 41
0x60 55 4F 0A 20 20 20 20 20 20 20 20 20 00 00 00 FE
0x70 00 42 31 32 35 48 41 4E 30 31 2E 30 20 0A 00 80

  

EDID ( Extended Display Identification Data) Report

Vendor/Product Identification:

Monitor Name :
Monitor Serial Number :
Manufacturer Name : AUO
Product Id : 106D
Serial Number : 0
Week Of Manufacture : 0
Year Of Manufacture : 2014
EDIDVersion : V1.4
Number Of Extension Flag : 0

Display parameters:

Video Input Definition : Digital Signal
DFP1X Compatible Interface : True
Max Horizontal Image Size : 280 mm
Max Vertical Image Size : 160 mm
Max Display Size : 12.7 Inches

Power Management and Features:

Standby : Not Supported
Suspend : Not Supported
ActiveOff : Not Supported
Video Input : 0
sRGB Default ColorSpace : False
Default GTF : Not Supported
Prefered Timing Mode : True

Gamma/Color and Etablished Timings:

Display Gamma : 2.2
Red : x = 0.587 - y = 0.35
Green : x = 0.342 - y = 0.585
Blue : x = 0.154 - y = 0.115
White : x = 0.305 - y = 0.32

Etablished Timings :

Display Type : Monochrome

Standard Timing:

Preferred Detailed Timing:

Pixel Clock : 152.6 Mhz

Horizontal Active : 1920 pixels
Horizontal Blanking : 310 pixels
Horizontal Sync Offset : 48 pixels
Horizontal Sync Pulse Width : 100 pixels
Horizontal Border : 0 pixels
Horizontal Size : 276 mm

Vertical Active : 1080 lines
Vertical Blanking : 60 lines
Vertical Sync Offset : 3 lines
Vertical Sync Pulse Width : 1 lines
Vertical Border : 0 lines
Vertical Size : 155 mm

Input Type : Digital Separate
Interlaced : False
VerticalPolarity : False
HorizontalPolarity : False

Monitor Range Limit:

Maximum Vertical Frequency : 0 Hz
Minimum Vertical Frequency : 0 Hz
Maximum Horizontal Frequency : 0 KHz
Minimum Horizontal Frequency : 0 KHz
Maximum Pixel Clock : 0 MHz

Stereo Display:

Stereo Display : Normal display (no stereo)

RAW Data:

0x00 00 FF FF FF FF FF FF 00 06 AF 6D 10 00 00 00 00
0x10 00 18 01 04 95 1C 10 78 02 6B A0 96 59 57 95 27
0x20 1D 4E 52 00 00 00 01 01 01 01 01 01 01 01 01 01
0x30 01 01 01 01 01 01 9C 3B 80 36 71 38 3C 40 30 64
0x40 31 00 14 9B 10 00 00 18 00 00 00 0F 00 00 00 00
0x50 00 00 00 00 00 00 00 00 00 20 00 00 00 FE 00 41
0x60 55 4F 0A 20 20 20 20 20 20 20 20 20 00 00 00 FE
0x70 00 42 31 32 35 48 41 4E 30 31 2E 30 20 0A 00 80

Thanks

Ben.

Ben

Do you have TEST2 pin high?

Thanks
David

Hi David , 

yes , TEST2 pin is high already.

Thanks

Ben.

Hi David ,
1)I have not understand why try set 0x5Ah to from 0x0C to 0x0D ?
Do you mean to try if this is a ASSR panel ?

2) if Quesiont (1) is right , Is test2 High OK ?

3) Do I need change below also:
<DSIInitSequence>
-23 FF 7 \n (remove)
-23 16 1 \n (remove)
-23 FF 0 \n (remove)
...
....
FF 0A \n
23 5A 5 \n (change to 5 from 4)
....
....
23 5A 0D \n (change to 0D from 0C )
4) Otherwise , if it might other issue but not ASSR problem, please help
pointout ?

Thanks
Ben.

Hi David ,
After try enable color bar mode of the reulst ASSR setting is not working , so I think this is NON-ASSR panel .

please help , thanks

Thanks
Ben.

Hi David ,
Color bar is working for ASSR or NON-ASSR setting.
Sorry , please forget above comment.

Hi David ,

Can you confirm again that both DSI0 & DSI1 connected to edp input is fine
for single mode of auo panel (1920x1080p) ?

please see following infomation from datasheet. :

Note: Unused DSI inputs pins on the SN65DSI86 should be left unconnected.
=============================================================
@ 0x10 Adresss

CHA_DSI_LANES
This field controls the number of lanes that are enabled for DSI Channel A.
00 = Four lanes are enabled
01 = Three lanes are enabled
10 = Two lanes are enabled
11 = One lane is enabled (default)
Note: Unused DSI inputs pins on the SN65DSI86 should be left unconnected.
RW
2:1
CHB_DSI_LANES
This field controls the number of lanes that are enabled for DSI Channel B.
00 = Four lanes are enabled
01 = Three lanes are enabled
10 = Two lanes are enabled
11 = One lane is enabled (default)
Note: Unused DSI inputs pins on the SN65DSI86 should

Thanks
Ben.

Ben

You can have both Channel A and B connected. But if only channel A is used, then you have to make sure you program I2C register for channel A only.

Thanks
David

Hi David ,

Can you please provide the DSIInitSequence of AUO panel  settings  (1920x1080/18bpp , single chanel , 2 edp) ? 

 

Vendor/Product Identification:

Monitor Name : 
Monitor Serial Number : 
Manufacturer Name : AUO
Product Id : 106D
Serial Number : 0
Week Of Manufacture : 0
Year Of Manufacture : 2014
EDIDVersion : V1.4
Number Of Extension Flag : 0

Display parameters:

Video Input Definition : Digital Signal
DFP1X Compatible Interface : True
Max Horizontal Image Size : 280 mm
Max Vertical Image Size : 160 mm
Max Display Size : 12.7 Inches

Power Management and Features:

Standby : Not Supported
Suspend : Not Supported
ActiveOff : Not Supported
Video Input : 0
sRGB Default ColorSpace : False
Default GTF : Not Supported
Prefered Timing Mode : True

Gamma/Color and Etablished Timings:

Display Gamma : 2.2
Red : x = 0.587 - y = 0.35
Green : x = 0.342 - y = 0.585
Blue : x = 0.154 - y = 0.115
White : x = 0.305 - y = 0.32

Etablished Timings :

Display Type : Monochrome

Standard Timing:

Preferred Detailed Timing:

Pixel Clock : 152.6 Mhz

Horizontal Active : 1920 pixels
Horizontal Blanking : 310 pixels
Horizontal Sync Offset : 48 pixels
Horizontal Sync Pulse Width : 100 pixels
Horizontal Border : 0 pixels
Horizontal Size : 276 mm

Vertical Active : 1080 lines
Vertical Blanking : 60 lines
Vertical Sync Offset : 3 lines
Vertical Sync Pulse Width : 1 lines
Vertical Border : 0 lines
Vertical Size : 155 mm

Input Type : Digital Separate
Interlaced : False
VerticalPolarity : False
HorizontalPolarity : False

Monitor Range Limit:

Maximum Vertical Frequency : 0 Hz
Minimum Vertical Frequency : 0 Hz
Maximum Horizontal Frequency : 0 KHz
Minimum Horizontal Frequency : 0 KHz
Maximum Pixel Clock : 0 MHz

Stereo Display:

Stereo Display : Normal display (no stereo)

RAW Data:

0x00 00 FF FF FF FF FF FF 00 06 AF 6D 10 00 00 00 00 
0x10 00 18 01 04 95 1C 10 78 02 6B A0 96 59 57 95 27 
0x20 1D 4E 52 00 00 00 01 01 01 01 01 01 01 01 01 01 
0x30 01 01 01 01 01 01 9C 3B 80 36 71 38 3C 40 30 64 
0x40 31 00 14 9B 10 00 00 18 00 00 00 0F 00 00 00 00 
0x50 00 00 00 00 00 00 00 00 00 20 00 00 00 FE 00 41 
0x60 55 4F 0A 20 20 20 20 20 20 20 20 20 00 00 00 FE 
0x70 00 42 31 32 35 48 41 4E 30 31 2E 30 20 0A 00 80

  

 

Ben

Attached is the calculated register value assume ASSR is not supported on this panel.

The register dump shows link training to be completed with no error. You can use DSI86 to read back the EDID info from the panel, can you please do that? I want to make sure the EDID read back by DSI86 match with the EDID info in the panel datasheet.

<aardvark>
<configure i2c=1 spi=1 gpio=0 tpower=1 pullups=0/>
<i2c_bitrate khz=100/>

======ASSR RW control ======
<i2c_write addr=0x2D count=1 radix=16> FF 7 </i2c_write>/>
<i2c_write addr=0x2D count=1 radix=16> 16 1 </i2c_write>/>
<i2c_write addr=0x2D count=1 radix=16> FF 0 </i2c_write>/>

======REFCLK Frequency ======
<i2c_write addr=0x2D count=1 radix=16> 0A 2 </i2c_write>/>

======DSI Mode ======
<i2c_write addr=0x2D count=1 radix=16> 10 26 </i2c_write>/>

======DSIA Clock ======
<i2c_write addr=0x2D count=1 radix=16> 12 44 </i2c_write>/>

======DSIB Clock ======
<i2c_write addr=0x2D count=1 radix=16> 13 44 </i2c_write>/>

======DP Datarate ======
<i2c_write addr=0x2D count=1 radix=16> 94 80 </i2c_write>/>

======Enable PLL ======
<i2c_write addr=0x2D count=1 radix=16> 0D 1 </i2c_write> <sleep ms=10/>

======Enable enhanced frame in DSI86 ======
<i2c_write addr=0x2D count=1 radix=16> 5A 4 </i2c_write>/>

======Number of DP lanes ======
<i2c_write addr=0x2D count=1 radix=16> 93 20 </i2c_write>/>

======Start Semi-Auto Link Training ======
<i2c_write addr=0x2D count=1 radix=16> 96 0A </i2c_write> <sleep ms=20/>

======CHA Active Line Length ======
<i2c_write addr=0x2D count=2 radix=16> 20 80 07 </i2c_write>/>

======CHB Active Line Length ======
<i2c_write addr=0x2D count=2 radix=16> 22 0 0 </i2c_write>/>

======Vertical Active Size ======
<i2c_write addr=0x2D count=2 radix=16> 24 38 04 </i2c_write>/>

======Horizontal Pulse Width ======
<i2c_write addr=0x2D count=2 radix=16> 2C 64 00 </i2c_write>/>

======Vertical Pulse Width ======
<i2c_write addr=0x2D count=2 radix=16> 30 01 00 </i2c_write>/>

======HBP ======
<i2c_write addr=0x2D count=1 radix=16> 34 A2 </i2c_write>/>

======VBP ======
<i2c_write addr=0x2D count=1 radix=16> 36 38 </i2c_write>/>

===== HFP ======
<i2c_write addr=0x2D count=1 radix=16> 38 30 </i2c_write>/>

===== VFP ======
<i2c_write addr=0x2D count=1 radix=16> 3A 03 </i2c_write>/>

===== DP-18BPP Disable ======
<i2c_write addr=0x2D count=1 radix=16> 5B 0 </i2c_write>/>

===== Color Bar Enable ======
<i2c_write addr=0x2D count=1 radix=16> 3C 07 </i2c_write>/>

===== Enhanced Frame, and Vstream Enable ======
<i2c_write addr=0x2D count=1 radix=16> 5A 0C </i2c_write>/>

</aardvark>

Thanks
David

Dear David , 

1) I found a mistake the calculation of DSI lanes might be wrong can you help confirm that  using Minimun number of DSI lanes  if 2 lane is OK ?

    ( The SDM850 platform's max bitclock is 1.2G much higher than DSI86 max support bitclock (750MHz) )

2)Below is the EDID &DPCD dump use DSI86 readback, can you please help us review  

--------------------------------------------------------
Dump Panel EDID
--------------------------------------------------------
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
--------------------------------------------------------
00| 00 FF FF FF FF FF FF 00 06 AF 6D 10 00 00 00 00
10| 00 18 01 04 95 1C 10 78 02 6B A0 96 59 57 95 27
20| 1D 4E 52 00 00 00 01 01 01 01 01 01 01 01 01 01
30| 01 01 01 01 01 01 9C 3B 80 36 71 38 3C 40 30 64
40| 31 00 14 9B 10 00 00 18 00 00 00 0F 00 00 00 00
50| 00 00 00 00 00 00 00 00 00 20 00 00 00 FE 00 41
60| 55 4F 0A 20 20 20 20 20 20 20 20 20 00 00 00 FE
70| 00 42 31 32 35 48 41 4E 30 31 2E 30 20 0A 00 80
--------------------------------------------------------
dump panel DPCD value
--------------------------------------------------------
DPCD 0000h: 11 0A 82 41 00 00 01 00 02 02 06 00 00 0B 00 00
DPCD 0100h: 0A 82 00 00 00 00 00 00 01 00 00 00 00 00 00 00
DPCD 0200h: 41 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00
DPCD 0210h: 00 00 00 00 00 00 00 00 00 0A 00 00 00 00 00 00

Thanks

Ben.

Ben

What is the clock frequency on DACP/N? If the clock frequency is 1.2G, it will not work with DSI86 as it exceeds DSI86 max supported clock frequency of 750MHz.

Your calculation is correct. The EDID dump also matches with the panel spec, so the eDP side look ok, the issue is more on the DSI side.

Thanks
David

Dear David , 

1)The combination of the settings.

       10h ->26  (single mode , 4 DSI lanes)
       12h ->44   (range 340~345hz)
       13h ->44   (range 340~345hz)  

the printout colok of DSIA  channel is 686394000hz , is that OK ?

2) Why not to set  address 12h to 0x89(685~690h) ? But , I already tried this setting to 0x89 , it's not work.

3)Can you help us confirm this panel is support ASSR from DPCD

   if this panel support:

     a. can we still test2 pin with high and how to configure?

     b. can this panel using nonASSR init sequence settings ?

Thanks.

Ben.

     

Ben

Register 0x13 has no effect since you are not using Channel B.

For Channel A, if you are using 2 lanes, then clock frequency is 688.6MHz, 0x12 needs to be programmed to be 0x89.

If you using 4 lanes, then clock frequency is 343.35MHz, and 0x12 needs to be programmed to be 0x44.

TEST2 needs to be pulled high in order for the SW to disable ASSR in order to support non-ASSR panel.

To disable ASSR, the instruction is
23 FF 7 \n
23 16 1 \n
23 FF 0 \n

If panel supports ASSR, then TEST2 can be tied to GND to disable the SW write. Or if TEST2 is tied high, then not writing to the register.

Does the color bar work with ASSR or non-ASSR panel?

What is the actual clock frequency being used in your system?

Since you are using Qualcomm, please use Qualcomm_ASSR or Qualcomm_noASS script.

Thanks
David