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DP83867IR: the receiver link down

haixing he
Prodigy 30 points
Part Number: DP83867IR


the DP83867 works  the 1000BASE-T speed. It's Transmitter is ok，we can receive all the packets by PC.But ,it's recieiver often link down, we read the register , the value is changed .it shows link is not established(add ress 0x0001),and  the local receiver is not OK(address 0x000a). the time  of the link down state is 30ms。

  • 0
    TI__Mastermind 19780 points

    Hi user,

    I need much more information than what you have provided to help with debug.  Please share the following information.

    schematic, and a log of all registers during link up, and when the link goes down.

    are you using Linux or some other operating system?

    can the link down be solved by resetting the PHY, or reconnecting the cable, and if the link stays up from that point on.

    Best Regards,

  • 0 in reply to Rob Rodrigues
    Prodigy 30 points

    Hi，

    I'am not using any operating system,I'am using the FPGA (cyclone IV )to control the phy  receiving and transmiting. the refclk of Phy is provided by FPGA.the Phy works in 1000BaseT.The MAC interface is GMII.

    When I start to transmit the data, the phy receiver can receive the data correctly almost. Sometimes  the receiver cannot receive any active signal within 30ms, The output of the signal( RXD ,RXDV, RXER) is 0 . 30ms later ,it will return normal state.

    the registers value in Link up state / Link down state:

    0x00: 0x1140 / 0x1140;   

    0x01:0x796D /0x7969; 

    0X02:0X2000 /0x2000; 

    0X03: 0XA231 /0xA231; 

    0X04: 0X0181 /0X0181; 

    0X05: 0XC181 /0XC181; 

    0X06:0X006D /0X006D; 

    0X07: 0X2001 /0X2001 ;

    0X08 : 0X48B2 /0X48B2;

    0X09: 0X1B00/0X1B00;

    0X0A: 0X7C00/0X4C00;

    0X0D: 0X401F/0X401F;

    0X0E: 0X0000/0X0000;

    0x0F: 0X3000/0X3000;

    0X10: 0X5048/0X5048;

    0X11: 0XAF02/0XAB02;

    0X12: 0X0000/0X0000;

    0X13:0X0000/0X0000;

    0X14: 0X2BC7/0X2BC7;

    0X15:0X0000/0X0000;

    0X16:0X0000/0X0000;

    0X17:0X0040/0X0040;

    0X1E:0X0002/0X0002;

    0X2D: 0X000D

    0X6E:0X5020;

    0X6F:0X0120;

    Best Regard.

  • 0 in reply to haixing he
    TI__Mastermind 19780 points
    Hi user,

    I see from your register dump that the master/slave 1000base-t manual configuration is being set in register 0x9 bit[12]. Are you intentionally setting this bit to 1 in your configuration? This can cause issues with 1000base-t links. Have you tried the data with register 0x9.12 set to 0?

    Also you mention the reference clock is provided by the FPGA. Have you attempted to use the reference clock from U18?

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 30 points

    Hi,

    When one DP83867 link with another DP83867, I will set on DP83867 in master mode ,another in slave mode.

    When  my acquisition system link with the PC,  the bit[12] in register 0x09 will  be set to 0,but the link down still happen.

    The register setting is Ok?

    Am I try to solve this problem in signal integrity or power integrity.

    The VDD1P1 power is supplied by  DC/DC ,and VDD2P5 power is supplied by LDO.

  • 0 in reply to haixing he
    TI__Mastermind 19780 points
    Hi user,

    How much ripple is on the VDD1P1 and the VDD2P5 supplies?

    Have you tried the link with the reference clock coming from U18? What is the voltage swing amplitude of the G1_REFCLK signal? Usually link instability is the result of reference clock issues like high jitter. FPGA sourced clocks often have high jitter that can cause link instability.

    You say after 30ms the link goes down... then 30ms later, the link returns. Does the link stay stable after this time? Does the link continue to toggle up and down? If the link only goes down once, I suspect some effect from software or other system effect.

    Register setting of 0x9 is OK, but not necessary. I would recommend not changing this unless necessary to system operation.

    Best Regards,