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SN65DSI86: dsi86 register setting

Terry Wu2
Expert 2110 points

Part Number: SN65DSI86

Hello Sirs,

We have a 4 lane MIPI to 2 lane eDP panel(1920x1200) inquiry using dsi86 .

Attach file is panel spec .

Would you help to provide register setting

1. color bar test setting

2. normal display setting

Is there eDP waveform . I am not sure the waveform we measure (test pattern) is ok or not . TKS !

ETML1010F8DHA Ver.1-RoHS.pdf

  • 0
    TI__Guru**** 183501 points
    Terry

    I would start with the Color Bar, get it to work first. Please use the spreadsheet I sent you for the DSI86 register setting. Once the color bar is working, then you can start the normal display setting by focusing on the MIPI interface.

    What pattern is this and what is the test condition?

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    Expert 2110 points

    Hi David,

    Thanks your help !

    We try test pattern on dsi86 EVM DP connector is OK ! Now we try test pattern on eDP panel is fail .

    But the DP signal is wire jump not by PCB layout + panel cable .

    Read the register address 0xf8 get "0x12" value

    - LT_EQ_LPCNT_ERR. This field is set whenever link training fails in the channel equalization phase

    due to the loop count being greater than five

    - LT_FAIL. This field is set whenever the Semi-Auto link training fails to train the DisplayPort Link.

    Another question is .

    If we don't feed REFCLK input .

    The DSI_CLK from SoC frequency must to be 384M,416M,460.8M,468M or 486M , right ?

    Can it be other different frequency ?

    TKS !

  • 0 in reply to Terry Wu2
    TI__Guru**** 183501 points
    Terry

    When using the REFCLK as the clock source, any DSI Clock frequency is supported, but if the clock source was instead the DSI A clock, then the required DSI Clock frequency would need to change to a frequency supported by the DSI86. When operating in this mode, any one of the following DSI A clock frequencies can be used: 384 MHz, 416 MHz, 460.8 MHz, 468 MHz, or 486 MHz.

    LT_FAIL indicates link training failure, this could due to the signal quality impact by the blue wire jump between the DP connector and panel cable. For semi-auto linking training, you can try to enable VOD and Pre-emphasis Level 3 by writing to DP Link Training LUT register, but without knowing the quality of the blue wire jump, even level 3 VOD and Pre-emphasis may not able to get link training to pass.

    Thanks
    David