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DS90UB913A-Q1: Unexpected behavior of serdes

na na78
Guru 16770 points
Part Number: DS90UB913A-Q1

Hi

Our customer made thier board and starts to evaluate it.
They faced some issues shown in attached file.

DS90UB913A_pulse_error.xlsx

-HD1 and HD2 are a signal of HSYNC.
-All DIN and ROUT are connected to ICs.
(Not shown in attached figure)
-Regarding to the signal of HD1/HD2,
T = 20.6usec and Pulse width = 20nsec.
-PCLK is 45MHz.
-Dfferential 100ohm termination at cable

Question
1. Why does not the pulse appear on deserializer output as expected? (Sheet of Error case 1)
2. Why does the pulse appear on deserializer output even if there is no pulse from serializer? (Sheet of Error case 2)

Could you see the cause of such behavior?

BestRegards

  • 0
    TI__Genius 10475 points
    Hello,
    The delays you are referring to are the serializer and deserializer data delays. Are you in 10-bit or 12-bit mode and why are using the typical value for serializer delay instead of max?
    Are you accounting for the channel delay? You need to pay attention to how the scope is set up to trigger the capture of the input/output pulses.
  • 0 in reply to Palaniappan Manickam
    Guru 16770 points
    Hi

    Thank you for your reply.

    It is examined in 12bit low freq mode.

    The cable delay is 23nsec. So tSD + sDD + cable delay would be ~2usec.

    As for the trigger, it is HD2 signal and it is triggered in following condition.

    - HD2 : Low is kept for longer than 25usec or
    - HD2 : Low is ended in shoter than 18usec

    HD1 is captured accompanied with HD2 at the same time.

    Could it be that the incorrect capturing is obtained?
    Or could it be possible to be error situation on the cable?

    BestRegards
  • 0 in reply to na na78
    TI__Genius 10475 points
    Hello,
    Please ensure it links up properly and LOCK stays high during the measurement. Do you have a block diagram of the system and the measurement setup?
    This can be related to the measurement setup or scope capture setup. Is this repeatable and is the behavior seen with different set of boards or cables? Is the scope in single event capture mode to record the HD1/HD2 pulses?
    Also as the datasheet specifies the tSD and tDD values are with default register settings with TRFB and RRFB set to '1'.
  • 0 in reply to Palaniappan Manickam
    Guru 16770 points
    Hi

    Thank you for your reply.

    The reason why the customer measures this signal is motivated by the operation error on the IC after deserializer.
    And there is no error on HD1. So I think something would have happened between DS90UB913A and DS90UB914A.

    The board of serializer side is image senser board including flash.
    The error 1 on the file I attached before happens at flashing operation.
    (Block diagram is not prepared, updating now)

    > Is this repeatable and is the behavior seen with different set of boards or cables?
    Yes. However, it is replicated only at flashing.

    >Is the scope in single event capture mode to record the HD1/HD2 pulses?
    Yes. It is triggered by HD2.

    In addition, TRFB and RRFB is set to 1 (default).


    >Please ensure it links up properly and LOCK stays high during the measurement.
    I confirmed that the LOCK of DS90UB914A moves to low in the error situation and back to high after a while.
    What is the reason that LOCK signal moves from high to low?

    BestRegrds
  • 0 in reply to na na78
    Guru 16770 points
    Hi

    Can I have your feedback?

    BestRegards
  • 0 in reply to na na78
    TI__Genius 10475 points
    Hello,

    >Please ensure it links up properly and LOCK stays high during the measurement.
    I confirmed that the LOCK of DS90UB914A moves to low in the error situation and back to high after a while.
    What is the reason that LOCK signal moves from high to low?

    >> This shows that the missing pulse behavior observed could be due to the link drop issue. The link can drop (LOCK low) if there are some system level issues such as power supply issues (excessive noise on the supplies, momentary drop of the supply etc) or PCLK quality issues such as excessive jitter, clock not stable or shift in frequency etc. You need to ensure these meet the datasheet specifications. Also check the quality of the cables between the SER and DES.
  • 0 in reply to Palaniappan Manickam
    Guru 16770 points
    Hi

    Thank you for your reply.
    I will check it.

    BestRegards