LVDS differential pair mismatch

Zeev Gerber

Intellectual 500 points

Hi,

I want to work with SPI over LVDS on long cable.

The clock frequency is low (10 MHZ).

what is the influence of LVDS differential pair mismatch over the cable/PCB/Driver asymmetrical?

Is it only an issue of slower rise/fall timing which make the maximum frequency to decrease??

could the signal integrity will decrease?

are there any limitation in the issue of functionality?

Pls. advise

Zeev Gerber

over 6 years ago

0 Yaser Ibrahim over 6 years ago

TI__Genius 10250 points

Hello,

Do you mean the differential pair length mismatch or impedance mismatch?

Regards,
Yaser

0 Zeev Gerber over 6 years ago in reply to Yaser Ibrahim

Intellectual 500 points

Hi,

I mean differential pair length mismatch.

Regards

Zeev Gerber

0 Yaser Ibrahim over 6 years ago in reply to Zeev Gerber

TI__Genius 10250 points

Hi Zeev,

The most significant effect of the length mismatch at such a low frequency is to cause the cross over point of the signals on differential pair to move up/down (instead of crossing at the halfway point). This negatively affects jitter and signal integrity . How much it affects it depends on the rise and fall times of the LVDS transceivers used more than the operating frequency. If the rise and fall times are longer, then more length mismatch can be tolerated. Since your frequency is low, you should be able to use LVDS transceivers with slower rise/fall times.

Regards,
Yaser

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LVDS differential pair mismatch