TIOL111: Power consumption & configuration of version without internal LDO

Hi Paul,

The version of this part without an LDO would have two power supply inputs - L+, which would power the higher-voltage interface, and VCC_IN, which would power the lower-voltage logic interface.

The current consumption from L+, excluding any load currents, can be seen in the I(L+) spec at the top of Table 6.5 in the datasheet. Multiplying this by the L+ voltage level would give the quiescent power dissipation for that portion of the circuit. If the device were configured to source current out of the CQ pin, this current would be drawn from L+ as well. The increase in power dissipation within TIOL111 could then be calculated by multiplying the load current by the voltage drop that occurs from L+ to CQ (this is specified as "residual voltage" in the datasheet).

The current consumption from VCC_IN is much lower - typically about 110 uA when the device is disabled (EN pin low) and 160 uA when enabled (EN pin high). This could be multiplied by the VCC voltage to compute the power dissipation in the logic circuitry.

Does this all make sense? Let me know if not.

Regards,
Max

Hi Max,
Thanks for the response and the explanation.
Is the VCC_IN consumption in the datasheet somewhere so I can reference it in my design notes?

Regards
Paul

Paul,

Unfortunately not - since the value was small enough to be negligible in most applications, it was not highlighted as a datasheet parameter and has not been fully characterized over all possible corner conditions.

Max