XIO2001 - PCIe Refclk recommended termination scheme for this clock when used in a Compact PCIe chassis?

Todd F

Other Parts Discussed in Thread: XIO2001

Per the XIO2001 PCIe bridge spec, the PCIe Refclk Vdiff input voltage is limited to 1.15V max swing.

See attachment

Does TI have a recommended termination scheme for this clock when used in a Compact PCIe chassis? Per the Compact PCIe standard section 3.1.1.6, this is a 3.3V LVPECL clock from the backplane, so it will have a Vdiff of ~1.4V. I can set the Vcm using an AC-coupled resistor divider, but that won't change the Vdiff swing level.

See attachment

7624.XIO2001 question.ppt

over 14 years ago

0 DJ Johnson over 14 years ago

TI__Prodigy 510 points

Gregory,

REFCLK, although an input, is spec'ed differently than the other receiver pairs. Having a VMax @1.4V should not be a problem, but we need to take a look at the REFCLK cell in question to be sure. We will confirm this on Monday.

0 Todd F over 14 years ago in reply to DJ Johnson

Intellectual 590 points

Just to clarify, the item the customer is concerned about is the Vrx-diff-pp (1.15V max). The understanding is that this is the swing of the differential input (Vp - Vn).

Todd

0 -DK- over 14 years ago in reply to Todd F

TI__Mastermind 27890 points

Todd,

Please let the customer know that there will be no problem with a 1.4V DIFF_PP on REFCLK.

Our documentation is in error here so we will work to update it.

EDIT: I have attached the relevant section from the PCIe specification to make this a bit more clear.

Thanks,

-DK

Interface

Interface forum

XIO2001 - PCIe Refclk recommended termination scheme for this clock when used in a Compact PCIe chassis?