TMDS171: Power up Timing

Koji-san

Please see this thread for my response: e2e.ti.com/.../2727410

Thanks
David

Hi David-san,

Thank you for your reply.

I understand the link training will be failed if the signal send while OE signal is ramping up.
On the other hand,what is happen if VDD is ramped up later than TD1(200us) after VCC ramp up.

Best Regards,
Koji Hamamoto

Hi David-san,

I have one more question.

If the link training is failed,which register should we check?　
As you mentioned before , 1Bh and 1Eh is BERT error counter bit.(1Ah is also error counter ,is that correct?)

Can we confirm whether the link training is failed or not failed at the register of 1Ah and 1Bh and 1Eh?

Best Regards,
Koji Hamamoto

Hi David-san,

>If OE is held low until VDD and VCC become stable there is no rail sequence requirement, so VDD can be powered up after VCC or VCC can be powered up after VDD.

Thank you. I understand.

>For TMDS, you can not use BERT counter as an indicator of link training failure.

If BERT counter can not use for a indicator of link training failure, what should we check to confirm the link training fail ?
HPD? or any other register?

Best Regards,
Koji Hamamoto

David-san,

Thanks!

Hi David-san,

I am sorry. May I ask one more question.

Does BERT counter(BERT_CNT) reset when the power downed? Or is it reset only when BERT_clr is set "1" or "0"?

Best Regards,
Koji Hamamoto

Koji-san

It should be the default value when power is removed.

Thanks
David