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DP83822I: Lowest possible power consumption.

Adrian Ball
Prodigy 20 points
Part Number: DP83822I

I'm currently designing the DP83822I into a new product. When system power fail is detected I want to quickly reduce the PHY power consumption to be as low as possible, in order to extend holdup time for the processor.

I'm running with 3.3V for both VDDIO and AVD. In the datasheet it states that maximum voltage on pins is 3.8V, and it seems this is irrespective of the VDDIO/AVD voltage.

Q1: So, when I detect a system power fail, is it ok to simply turn off VDDIO and AVD, leaving input signals such as TX_EN and RESET still driven to 3.3V by the processor?

Q2: If that's NOT ok, what is the power consumption of the chip with RESET driven low?

  • 0
    TI__Mastermind 26320 points
    Hi Adrian,

    We suggest configuring DP83822 in Deep Power Down state. Datasheet provides power consumption for various AVDD/VDDIO in this state. Alternatively you can use RESET as well, expect similar power consumption in this state as well.

    We don't recommend switching off VDDIO and AVD while driving TX_EN and RESET as these are not fail safe IOs.

    Regards,
    Geet
  • 0 in reply to Geet Modi
    Prodigy 20 points
    Hi Geet,
    Thanks. I think RESET is the way to go. I don't really want to involve the processor in the early stages of power fail, as it has enough other things to look after. Hence I don't want to use the PWDN pin either, as we are using it as an interrupt output and to switch modes would once again require processor activity.
    But if RESET will give me similar power consumption as Deep Power Down, I think that will be good enough!
    Cheers,
    Adrian.