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Linux/DP83TC811R-Q1: DP83TC811R-Q1 linux driver porting issue

Part Number: DP83TC811R-Q1
Other Parts Discussed in Thread: DP83TC811

Tool/software: Linux

Hi Ti Engineer,

I meet some questions when porting the DP83TC811R linux driver to my target(s32v234,kernel verson:4.1).

I config the device tree to support 802.3-c45(e.g.compatible = "ethernet-phy-ieee802.3-c45";).But the kernel can't attach the phy device.

I trace the phy driver code in phy_device.c.There is the follow  segment:

I read the phy_reg(reg_addr = MII_ADDR_C45 | i << 16 | MDIO_DEVS2,reg_addr = MII_ADDR_C45 | i << 16 | MDIO_DEVS1) is always 0 and c45_ids->devices_in_package is also 0.

so when probing Device Identifiers ,it can not execute the process.

/**
* get_phy_c45_ids - reads the specified addr for its 802.3-c45 IDs.
* @bus: the target MII bus
* @addr: PHY address on the MII bus
* @phy_id: where to store the ID retrieved.
* @c45_ids: where to store the c45 ID information.
*
* If the PHY devices-in-package appears to be valid, it and the
* corresponding identifiers are stored in @c45_ids, zero is stored
* in @phy_id. Otherwise 0xffffffff is stored in @phy_id. Returns
* zero on success.
*
*/
static int get_phy_c45_ids(struct mii_bus *bus, int addr, u32 *phy_id,
struct phy_c45_device_ids *c45_ids) {
int phy_reg;
int i, reg_addr;
const int num_ids = ARRAY_SIZE(c45_ids->device_ids);

/* Find first non-zero Devices In package. Device
* zero is reserved, so don't probe it.
*/
for (i = 1;
i < num_ids && c45_ids->devices_in_package == 0;
i++) {
reg_addr = MII_ADDR_C45 | i << 16 | MDIO_DEVS2;
phy_reg = mdiobus_read(bus, addr, reg_addr);
if (phy_reg < 0)
return -EIO;
c45_ids->devices_in_package = (phy_reg & 0xffff) << 16;

reg_addr = MII_ADDR_C45 | i << 16 | MDIO_DEVS1;
phy_reg = mdiobus_read(bus, addr, reg_addr);
if (phy_reg < 0)
return -EIO;
c45_ids->devices_in_package |= (phy_reg & 0xffff);

/* If mostly Fs, there is no device there,
* let's get out of here.
*/
if ((c45_ids->devices_in_package & 0x1fffffff) == 0x1fffffff) {
*phy_id = 0xffffffff;
return 0;
}
}

/* Now probe Device Identifiers for each device present. */
for (i = 1; i < num_ids; i++) {
if (!(c45_ids->devices_in_package & (1 << i)))
continue;

reg_addr = MII_ADDR_C45 | i << 16 | MII_PHYSID1;
phy_reg = mdiobus_read(bus, addr, reg_addr);
if (phy_reg < 0)
return -EIO;
c45_ids->device_ids[i] = (phy_reg & 0xffff) << 16;

reg_addr = MII_ADDR_C45 | i << 16 | MII_PHYSID2;
phy_reg = mdiobus_read(bus, addr, reg_addr);
if (phy_reg < 0)
return -EIO;
c45_ids->device_ids[i] |= (phy_reg & 0xffff);
}
*phy_id = 0;
return 0;
}

  • Hi,

    It appears that driver is not able to access MDIO interface to read phy registers. You may need to perform basic checks that Phy is out or reset.

    1. You can look at RX_CLK pin whether clock is provided or not ?
    2. Check MDIO has pull-up to VDDIO.

    Regards,
    Geet
  • Hi Geet,

    The RX_CLK signal is disconnected because my target is RMII Mode.

    And I can read the phy_id=0x2000a253 when I delete the follow source code segment:

    /* Now probe Device Identifiers for each device present. */
    for (i = 1; i < num_ids; i++) {
    if (!(c45_ids->devices_in_package & (1 << i)))
    continue;

    So I confirm that phy registers are accessed.

    I read the DP83Tc811 phy registers under u-boot . The result isfollow:

    U-Boot 2016.01-00001-g3485462-dirty (Nov 19 2018 - 08:56:42 +0800)

    CPU: NXP S32V234 V2.0 at 1000 MHz
    Reset cause: unknown reset
    Board: s32v234evb29288
    I2C: ready
    DRAM: 2 GiB
    All (4) cores are up.
    MMC: FSL_SDHC: 0
    *** Warning - bad CRC, using default environment


    Forcing PCIe to Gen1 operation
    phy link never came up
    DEBUG_R0: 0x00c50d00, DEBUG_R1: 0x08200000
    In: serial
    Out: serial
    Err: serial
    The security module (CSE3) is disabled.
    Net:
    Warning: System is using default MAC address. Please set a new value
    FEC
    Hit any key to stop autoboot: 0
    =>
    =>
    =>
    =>
    => mii read 0x00 0x00006
    0000
    => mii read 0x00 0x0005
    0000
    => mii read 0x00 0x0003
    A253
    => mii read 0x00 0x0002
    2000
    =>

    Thanks a lot!

  • Hi,

    That's good that Phy is alive. Instead of RX_CLK, can you probe CLK_OUT on pin 16 ?

    Also, I need you to dumpe following register on both DUT and Link Partner and share.

    Register 0x00 to 0x31, 0x467

    regards,
    geet
  • Hi,

    I am closing this thread. Incase you need further assistance, kindly open new thread and provide link to this thread.

    Regards,
    Geet