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TUSB1064: The definition of TUSB1064

Part Number: TUSB1064
Other Parts Discussed in Thread: TPS65987D

Regarding to TUSB1064 design documents, recently we encountered a serious problems on our board,  

The definition of pin 4, 5, 7, and 8 of TUSB1064 on TI datasheet and EVM Schematic is opposite, (TUSB1064 in GPIO mode)

please refer to attached file for the detail.TUSB1064.xlsx

  • Dennis

    What issue are you seeing on your board?

    The EVM schematic needs to be corrected to match with the datasheet. But USB3 supports polarity swap on both SSTX and SSRX.

    Thanks
    David
  • Hi, David,

    The symptom is USB3.1 cannot work on our board.
    By the way, how to enable the polarity swap function of USB3 on both SSTX and SSTX? Is it enabled by register?
    Thanks
    Dennis
  • Dennis

    Lane polarity swap is part of the USB spec as part of the handshaking process. For Gen 1, it uses TSEQ Ordered set and for Gen 2, it uses SYNC ordered set. 

    Are you in GPIO or I2C mode?

    Please check the voltage on CTL0, CTL1, and FLIP, make sure CTL0 is high, and CTL1 is low for USB mode. 

    Please then check SSTX and SSRX to see if LFPS is being sent from both the host and source. 

    Would you please send me your schematic?

    Thanks

    David

  • David,

    Thanks for your information, we're in GPIO mode, and we'll check the CTL0, CTL1, and FLIP first.

    Regarding to the schematic file, actually Alec Chen had sent to you on 11/9 via E2E with title "TUSB1064: USB3.0/DP Issue with TPS65987D+TUSB1064 on the sink side".
    Thanks
    Dennis