I’m in the process of setting up the TCAN4550-Q1 and I’m having a hard time understanding the Interrupt settings. I’m using the SLLSEZ5 – JANUARY 2018 – REVISED MAY 2018 of the datasheet. My goal is to setup GPIO1 to interrupt if a message is received in either FIFO1 or FIFO0 and GPO2 to interrupt after a Transmission is complete.
Here are the settings that I’m programming:
Address: Value
0x0800 0x084404A2
0x1050 0x00000000
0x1054 0x00000211
0x1058 0x00000011 (TX complete is assigned to m_can_int0 and both RX
interrupt are assigned to m_can_int1)
0x105C 0x00000003
Does this look correct?
When either a new message is received, or a message is transmitted, does register 0x1050 need to be written with 0x0000 0000 to allow the pins to return High and reset the interrupt flags?
Thanks,
Joe
