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SN65DSI85: SN65DSI85

Vijay Kumar76561
Prodigy 190 points
Part Number: SN65DSI85

Hi,

We are using SN65DSI85 for single DSI to single LVDS, i.e. we are using Channel A to Channel

The panel resolution info is as below:

HTotoal = 1648 = [1280(Active) + 80(HPW) + 216(HBP) + 72(HFP)]

VTotoal = 750 = [720(Active) + 5(VPW) + 22(VBP) + 3(VFP)]

Frame rate = 60Hz

We are using ref clock as 74.25. *** DSI CLK is not used for generating LVDS clock******

We see the test pattern being displayed on the panel correctly. However garbage is being displayed when we drive data from DSI. Attached is the snapshot of what it looks like.

Also attached is the register dump. Can you please let us know if we are doing something wrong!!

Fullscreen register_dump.config Download 
[0x9] -> [0x0]
[0xa] -> [0x84]
[0xb] -> [0x0]
[0xd] -> [0x1]
[0x10] -> [0x20]
[0x11] -> [0x0]
[0x12] -> [0x2c]
[0x13] -> [0x0]
[0x18] -> [0x1a]
[0x19] -> [0x0]
[0x1a] -> [0x3]
[0x1b] -> [0x0]
[0x20] -> [0x0]
[0x21] -> [0x5]
[0x22] -> [0x0]
[0x23] -> [0x0]
[0x24] -> [0xd0]
[0x25] -> [0x2]
[0x26] -> [0x0]
[0x27] -> [0x0]
[0x28] -> [0x20]
[0x29] -> [0x0]
[0x2a] -> [0x0]
[0x2b] -> [0x0]
[0x2c] -> [0x50]
[0x2d] -> [0x0]
[0x2e] -> [0x0]
[0x2f] -> [0x0]
[0x30] -> [0x5]
[0x31] -> [0x0]
[0x32] -> [0x0]
[0x33] -> [0x0]
[0x34] -> [0xd8]
[0x35] -> [0x0]
[0x36] -> [0x16]
[0x37] -> [0x0]
[0x38] -> [0x48]
[0x39] -> [0x0]
[0x3a] -> [0x3]
[0x3b] -> [0x0]
[0x3c] -> [0x0]
[0x3d] -> [0x0]
[0x3e] -> [0x0]
[0xe0] -> [0x0]
[0xe1] -> [0x0]
[0xe2] -> [0x0]
[0xe5] -> [0x1]
[0xe6] -> [0x0]

Regards,

Vijay

  • 0
    Prodigy 190 points

    Hi,

    Just wanted to add further information that were input to the DSI tuner tool.

    Please find the screen shot of the same. Also please find attached, the  CSR register contents generated by the tool.

    Fullscreen CSR_REF.txt Download 
    //=====================================================================
// Filename   : CSR_REF.txt
//
//   (C) Copyright 2013 by Texas Instruments Incorporated.
//   All rights reserved.
//
//=====================================================================
0x09              0x00
0x0A              0x04
0x0B              0x00
0x0D              0x00
0x10              0x26
0x11              0x00
0x12              0x2c
0x13              0x00
0x18              0x7a
0x19              0x00
0x1A              0x03
0x1B              0x00
0x20              0x00
0x21              0x05
0x22              0x00
0x23              0x00
0x24              0x00
0x25              0x00
0x26              0x00
0x27              0x00
0x28              0x20
0x29              0x00
0x2A              0x00
0x2B              0x00
0x2C              0x50
0x2D              0x00
0x2E              0x00
0x2F              0x00
0x30              0x05
0x31              0x00
0x32              0x00
0x33              0x00
0x34              0xd8
0x35              0x00
0x36              0x00
0x37              0x00
0x38              0x00
0x39              0x00
0x3A              0x00
0x3B              0x00
0x3C              0x00
0x3D              0x00
0x3E              0x00


The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the recommended sequence defined in the datasheet
    he tool.

    Regards,

    Vijay

  • 0 in reply to Vijay Kumar76561
    TI__Mastermind 35130 points

    Hi Vijay,

    Are you supplying the device with a 222.75 MHz DSI CLK? You still need a DSI CLK regardless of whether or not you use an external reference clock when you're using real DSI data and not just the test pattern.

    Regards,
    I.K.

  • 0 in reply to Ikechukwu Anyiam
    Prodigy 190 points

    Hi I K ,

    Thanks for the quick response.

    Yes, we are supplying DSI clock during data transfer.

    Is it possible to confirm if the registers are set properly for the given panel and DSI information. I believe I have provided all the necessary things as snapshot in the earlier ticket.

    Is there anything special to consider when we are using reference clock.,  instead of DSI clock?

    Any input in this regard is appreciated.

    Regards,

    Vijay

  • 0 in reply to Vijay Kumar76561
    TI__Mastermind 35130 points
    Hi Vijay,

    The register dump looks okay, except that I can see bit 0 in error register 0xE5 being set, indicating a PLL_UNLOCK error. Please check the following items for me:

    1. Ensure that you are following the initialization sequence on page 17 of the datasheet. It is critical that you follow this sequence for correct operation of the device.

    2. Check that the video data provided by the DSI source (clock frequency, active data, blanking data, etc.) matches what you are programming in the DSI85.

    3. Check that the REFCLK is within specification of the electrical and switching characteristics listed in the datasheet.

    Please also share the datasheet for your panel. You can email it to i-anyiam@ti.com if you do not want to share it here. Note that this issue will continue to be supported on this E2E thread and not over email though.

    You can also reference this application note and video for additional debugging tips:
    www.ti.com/.../slla356.pdf
    www.youtube.com/watch

    Regards,
    I.K.
  • 0 in reply to Ikechukwu Anyiam
    Prodigy 190 points

    Hi I K,

    Thanks for your inputs on confirming that the settings were fine.

    We found that, there was a short on one of the dsi lines, which was causing the issue.

    With that resolved, we are able to display dsi data on the display. However, we are noticing that there is lots of noise on the display. Only the black and white pixels are shown properly. For the rest, it seems as if the colors are smeared on the display.

    We are yet to spend more time on the issue to get a hang of what's going on. We might need your help in near future.

    Just a question - we are able to see test pattern properly from bridge chip on the display, where as the dates from dsi seems like as if it's smeared. Since test pattern is fine, can we assume that bridge chip registers settings are fine?

    Regards,

    Vijay

  • 0 in reply to Vijay Kumar76561
    TI__Mastermind 35130 points
    Hi Vijay,

    Sorry for the delay it looks like I missed your reply. Are you still having issues? To answer your question, if you can get the test pattern to display properly then the register settings are probably fine, and the issue is most likely on the DSI side.

    Regards,
    I.K.
  • 0 in reply to Ikechukwu Anyiam
    TI__Mastermind 35130 points
    Hi Vijay,

    Is this issue still open?

    Regards,
    I.K.
  • 0 in reply to Ikechukwu Anyiam
    Prodigy 190 points

    Hi I.K,

    Apologies for not responding earlier.

    This issue is addressed. Thanks for your continued support. 

    We had to change certain settings on DSI host side and also few register settings on TI side.

    Regards,

    Vijay