DS90UB954-Q1: I2C issues

Nao

Part Number: DS90UB954-Q1

Hi, E2E members,

Our customer is evaluating DS90UB954 and DS90UB953.
New they are evaluating I2C communication to DS90UB953 from DS90UB954 to use a back channel.
Their I2C communiaction way is here.

MCU -- I2C --> DS90UB954 -- FPD BackChannel (I2C) --> DS90UB953

DS90UB954 resister setting has no problem. But the failure to set register of DS90UB953 from MCU.

And then, they are facing the following I2C issues.
Sometimes DS90UB954 send NACK or long clock strech (>5ms), when MUC is setting DS90UB953 registers from I2C.

Q1. Does DS90UB954 return NACK for I2C access to Serializer via BackChannel due to the reason of DS90UB954?

Q2-1. Is there a timing when the DS90UB953 refuses I2C access via BackChannel?

Q2-2. If Q2 is yes. What is the situation when DS90UB953 answers NACK for I2C access via BackChannel?

Q3. Is there a way to confirm from the DS90UB954 side that the DS90UB953 can not respond to I2C access?

Regards,
Nao

over 7 years ago

0 Michael.Walker over 7 years ago

TI__Mastermind 19720 points

Hello Nao,

Can you please confirm that the 954 and 953 are locked during these issues? If the link is intermittent, this could also cause problems with remote I2C transactions.

Q1. Does DS90UB954 return NACK for I2C access to Serializer via BackChannel due to the reason of DS90UB954?

Please verify that the serializer is configured properly, Register 0x5C on the 954. The MCU should be writing to the serializer alias not the serializer ID. If I2C pass-through is not enabled on the deserializer the I2C transaction will be sent across the back channel. Please verify that register 0x58 bit 6 on the 954 is set to 1.

Q2-1. Is there a timing when the DS90UB953 refuses I2C access via BackChannel?
Q2-2. If Q2 is yes. What is the situation when DS90UB953 answers NACK for I2C access via BackChannel?

It is possible to disable remote writes to the 953 registers by setting LCL_WRITE_DISABLE (0x08[7]) to 1. However, this bit must be set locally on the 953 side, so I doubt that this is the cause of your issues. Nonetheless, please verify that 0x08[7] is set to 0 on the 953.

Q3. Is there a way to confirm from the DS90UB954 side that the DS90UB953 can not respond to I2C access?

There is no specific register that monitors this, as the host controller can detect this issue itself.

Michael W.

0 Nao over 7 years ago in reply to Michael.Walker

Genius 4905 points

Hi, Michael

Thank you for your quick reply.
Sorry. I didn't write the important things.

This issues happen time to time.
So, I guess our setting that are DS90UB954 and DS90UB953 is right, because it's sometimes work well.

Do you have any ideas for this situation?

Regards,
Nao

0 Michael.Walker over 7 years ago in reply to Nao

TI__Mastermind 19720 points

Hi Nao,
This might be a signal integrity issue. Can you please confirm that the 954 and 953 are locked during these issues? you can verify this checking the LOCK pin on the 954.

-Michael W.

0 Nao over 7 years ago in reply to Michael.Walker

Genius 4905 points

Hi, Michael

Thank you for your quick feedback about my questions.
Sure, your suggestion is one of several possibilities.
I will tell my customer your advice.

I bring back, if I need more help.

Regards,
Nao

0 Michael.Walker over 7 years ago in reply to Nao

TI__Mastermind 19720 points

Hi Nao,
No Problem, It is also very helpful in debugging your system if you could give us the all of the register values for the 953 and 954.
Regards,
Michael W.

0 Nao over 7 years ago in reply to Michael.Walker

Genius 4905 points

Hi, Michael

Update of this issue.
Our customer is evaluating two systems.
First is the using Coax cable. It is good and doesn't problem.
Second is the using STP cable. They are facing this issue.
Two difference is only the using type of cable.
#1 Have you ever faced the same problem?

STP cable system has I2C miss comunication everytime.
They are measuring LOCK pin waveforme now.
Please give me some time before I send this result.

Our customer has one question about tDDLT (Deserializer data lock time).
According to the DS90UB954 datasheet tDDLT MAX is 300ms.
This condition is the coaxial cable.
#2 Does this value change, when we use STP cable?

Regards,
Nao

0 Michael.Walker over 7 years ago in reply to Nao

TI__Mastermind 19720 points

Hello Nao,

Can you share the 954 and 953 schematic with STP cable and with Coax cable? specifically I need the capacitor values on the FPD data lines.

1. I have not come across this situation before.
2. no it should not change.

0 Nao over 7 years ago in reply to Nao

Genius 4905 points

Hi, Michael

Thank you for your reply.
I will ask my customer to share their schematics.

Regards,
Nao

0 Nao over 7 years ago in reply to Michael.Walker

Genius 4905 points

Hi, Michael

Thank you for your reply.
I will ask my customer to share their schematics.
I bring back, if I need more help.

Regards,
Nao

0 Nao over 7 years ago in reply to Nao

Genius 4905 points

Hi, Michael

Thank you for your reply.
I will ask my customer to share their schematics.

Regards,
Nao

0 Nao over 7 years ago in reply to Nao

Genius 4905 points

Hi, Hichael

Our customer has 2 more questions about tDDLT (Deserializer data lock time) and LOCK_STS bit.

#1. According to the Fig57 and 58, 954 Lock Time looks line different value.
Is "954 Lock Time" and "tDDLT" the same value?
If yes.
Does that mean "954 Lock Time(tDDLT)" falls below 300 ms?
If no.
What is "954 Lock Time"?

#2. Please let me know the condition, that the status of the LOCK signal is reflected in bit 0 of the 0x4D register of UB954.
I want to know about judgment function.
For example,
An edge of a signal is detected.
"1" if it is HIGH for a fixed time, and "0" if it is LOW for a fixed time. etc...

Regards,
Nao

PS.
Our customer checking the LOCK pin on the 954.
Please wait for a little while longer. Thanks.

0 Michael.Walker over 7 years ago in reply to Nao

TI__Mastermind 19720 points

Hello Nao,

"Is "954 Lock Time" and "tDDLT" the same value? "
954 Lock Time and tDDLT are the same thing.

"#2. Please let me know the condition, that the status of the LOCK signal is reflected in bit 0 of the 0x4D register of UB954.
I want to know about judgment function.
For example,
An edge of a signal is detected.
"1" if it is HIGH for a fixed time, and "0" if it is LOW for a fixed time. etc..."

The register will be updated every time there is a change to the LOCK status. it will not hold the register high or low for a fixed time period.

-Michael W.

0 Nao over 7 years ago in reply to Michael.Walker

Genius 4905 points

Hi, MIchael

> 954 Lock Time and tDDLT are the same thing.
Does that mean "954 Lock Time(tDDLT)" falls below 300 ms?

> The register will be updated every time there is a change to the LOCK status.
> it will not hold the register high or low for a fixed time period.
Please tell me the conditions under which the LOCK PIN status changes to hi?

Regards,
Nao

0 Michael.Walker over 7 years ago in reply to Nao

TI__Mastermind 19720 points

Hello Nao,

>Does that mean "954 Lock Time(tDDLT)" falls below 300 ms?
Yes

>Please tell me the conditions under which the LOCK PIN status changes to hi?
The LOCK pin will be high when ever the de-serializer is locked on to the serializer. This means that if the bit is intermittently locking and unlocking the LOCK pin will be intermittently going low and high.

0 Nao over 7 years ago in reply to Michael.Walker

Genius 4905 points

Hi, Michael

Thank you for your reply.
I will tell our customer your answer.

Our customer checking the LOCK pin on the 954...
Please wait for a little while longer. Thanks.
I hope you understand the delay of checking LOCK pin status.

Regards,
Nao

0 Michael.Walker over 7 years ago in reply to Nao

TI__Mastermind 19720 points

Hello Nao,

No problem, Also please provide the capacitor values on the FPD-link lines of both systems.

Regards,
Michael W.

0 Nao over 7 years ago in reply to Michael.Walker

Genius 4905 points

Hi Michael

Are those capacitor values the following fig?
Is my understanding right?

ex) UB953 EVM

ex) UB954 EVM

Of course, I understand that we need our customer conditions of the using STP cable.

Regards,
Nao

0 Nao over 7 years ago in reply to Nao

Genius 4905 points

Hi Michael

Do you want to check this?

Regards,
Nao

0 Michael.Walker over 7 years ago in reply to Nao

TI__Mastermind 19720 points

Hi Nao,

Yes, those are the capacitor values that I would like to check. Are both of your applications in Synchronous or in Non-Synchronous mode?

Regards,
Michael W.

0 Nao over 7 years ago in reply to Michael.Walker

Genius 4905 points

Hi, Michael

Thank you for your reply.

My and our customer's AI list is here.

1. Checking LOCK pin status for the checking FPD-Link signal quality.
- Our customer is checking the LOCK pin on the 954 now...
2. Send to you the customer's schematics, if I get it and accept our customer to send it you.
3. Checking customer system conditions.
- Checking the capacitor values on the FPD-Link line.
- Using Synchronous or Non-Synchronous mode?

anythis else?
let me know, if you need more information.

Regards,
Nao

0 Michael.Walker over 7 years ago in reply to Nao

TI__Mastermind 19720 points

Hello Nao,

That should be enough information for now.

Regards,
Michael W.

0 Nao over 7 years ago in reply to Michael.Walker

Genius 4905 points

Hello Michael,

Sorry for not send my AI information but my customer has some questions.

#1. Continue from LOCK system question. They want to know more detail about that.
What conditions of FPD-Link signal that the LOCK pin goes to hi?

#2 Continue from tDDLT (Deserializer data lock time) question.
Does the value of tDDLT change with the following conditons?
NOTE: It is not MAX time but current time.
Case1. using COAX.
Case2. using STP.

I guess this answer is YES. However, MAX time is 300 ms or less.

I guess our customers system that is using STP that does NOT LOCK before access to the serializer with I2C.
BUT, their system that is using COAX that CAN LOCK on the same condition.
So, they want to know the difference of the tDDLT time that COAX and STP.

About I2C question... It is I guess ... too.
Our customer is planning to add the checking sequence of LOCK status with 0x4D:0bit (LOCK_STS) by SW.
So, they want to know the detail of LOCK conditions.

Hence, I guess this issues is not a HW problem.

Regards,
Nao

0 Michael.Walker over 7 years ago in reply to Nao

TI__Mastermind 19720 points

Hello Nao,

>#1. Continue from LOCK system question. They want to know more detail about that.
>What conditions of FPD-Link signal that the LOCK pin goes to hi?

The deserializer will Pull the LOCK pin high when the deserializers PLL is locked on to the serializers signal. the deserilizers LOCK pin will stay high until the PLL loses lock then the LOCK pin will go low.

>#2 Continue from tDDLT (Deserializer data lock time) question.
>Does the value of tDDLT change with the following conditons?
>Case1. using COAX.
>Case2. using STP.

No, the tDDLT value does not change with cable type.

I suspect that there is something different between their systems with the two different cables that is causing the devices to not have a good connection(e.g wrong cap value, bad high speed layout, bad cable).

Regards,
Michael W.

0 Nao over 7 years ago in reply to Michael.Walker

Genius 4905 points

Hello Michael

Thank you for your update.
> No, the tDDLT value does not change with cable type.
I understand it.
According to the D/S, tDDLT has the TYP and MAX value.
Does it mean this value changed due to the influence of the AEQ range?
If yes,
Do you think that the value of AEQ changes as the cable changes and then the value of tDDLT changes?
I think that there is also the influence of system design as you say.

Regards,
Nao

0 Michael.Walker over 7 years ago in reply to Nao

TI__Mastermind 19720 points

Hello Nao,

>I understand it.
>According to the D/S, tDDLT has the TYP and MAX value.
>Does it mean this value changed due to the influence of the AEQ range?
>If yes,
>Do you think that the value of AEQ changes as the cable changes and then the value of tDDLT changes?
>I think that there is also the influence of system design as you say.

The tDDLT does vary a little bit in every system due to AEQ but it is always going to be under the MAX value.

Does your customer think that this has anything to do with their issue? why would they think that?

Thank you,
Michael W.

0 Nao over 7 years ago in reply to Michael.Walker

Genius 4905 points

Hi, Michael

Sorry for confusing you.
My customer question is simple.
They want to know not difference of MAX time but difference of current time.

Ex)
Case1. using COAX. tDDLT is 150ms.
Case2. using STP. tDDLT is 170ms.
NOTE: These time are not measurement data on customer board.

Why is STP's time longer than COAX's time?
Is the reason the difference of cables?
Is the reason the difference of other points?

Regards,
Nao

0 Michael.Walker over 7 years ago in reply to Nao

TI__Mastermind 19720 points

Hello Nao,
They the tDDLT should not differ because of the cable type(STP vs Coax) but because of the the cable signal integrity quality and cable length.

Thank you,
Michael W.

0 Nao over 7 years ago in reply to Michael.Walker

Genius 4905 points

Hi, Michael

Thank you for your quick reply.
I will update it to our customer.

Regards,
Nao

0 Michael.Walker over 7 years ago in reply to Nao

TI__Mastermind 19720 points

Hello Nao,
Is there any updates from your customer?
-Michael W.

0 Nao over 7 years ago in reply to Michael.Walker

Genius 4905 points

Hi, Michael

Our customer changed the I2C timing.
And then, They were able to write register with I2C.
So, we close this E2E. Thank you very much.

Regards,
Nao

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DS90UB954-Q1: I2C issues