DP83867IS: Help double check the schematic

Hi Rob,

Many thanks for the support! We did the modification according to your suggestion on schematic. Customer is using NXP's MCU, but they can't use the driver you posted above due to different platform.

Now customer can use MDIO interface to read and write registers of DP83867IS. And they can also use the TEST mode and tested the TEST waveform, which is good. But the issue is that DP83867IS can't link with the partner(Like the PC side, We double confirm that the link partner works well). Also we tested that the SIN/SIP and SON/SOP do have waveform, while these are no waveform on TD_P/M_A/B/C/D.

We read out the registers, as below:

read phy addr: 0x8  reg: 0x0   value : 0x1140

read phy addr: 0x8  reg: 0x1   value : 0x7949 

read phy addr: 0x8  reg: 0x2   value : 0x2000

read phy addr: 0x8  reg: 0x3   value : 0xa231 

read phy addr: 0x8  reg: 0x4   value : 0xd41

read phy addr: 0x8  reg: 0x5   value : 0x0   
 read phy addr: 0x8  reg: 0x6   value : 0x64  

read phy addr: 0x8  reg: 0x7   value : 0x2001    

read phy addr: 0x8  reg: 0x8   value : 0x0  

read phy addr: 0x8  reg: 0x9   value : 0x200 

read phy addr: 0x8  reg: 0xa   value : 0x0  

read phy addr: 0x8  reg: 0xb   value : 0x0  

read phy addr: 0x8  reg: 0xc   value : 0x0   

read phy addr: 0x8  reg: 0xd   value : 0x0 

read phy addr: 0x8  reg: 0xe   value : 0x0 

read phy addr: 0x8  reg: 0xf   value : 0x3000

read phy addr: 0x8  reg: 0x10   value : 0x5848

Now we are debugging on this issue and urgently need your support, Can you help review above registers and provide support(Suggestions to move ahead and solve this issue)? Thanks a lot!

Best regards,

Sulyn

Hi Sulyn,

Ethernet troubleshooting should be handled in 2 steps:
1. Verify HW (PHY layer only)
1.a.Do not use SW tools like PING to verify HW layer
2. Verify SW (Linux or other SW driver as necessary)
2.a. Connect to MAC
2.b. Use ping to verify upper layers

To verify the hardware:
Starting with NO connection to link partner.
1. measure the supply pins
1.a. Verify they are in datasheet specs
2. Ensure the reference clock is OK
2.a. 25MHz +/-100ppm as measured at the CLK_OUT pin
3. Ensure the reset is being released as per datasheet
4. Measure voltage on RBIAS resistor
4.a. for DP83867, this voltage should be 1.0V
5. Measure waveform on TD_P_A/TD_M_A using a 100ohm load and a differential probe.
5.a. In auto-negotiation mode you should see the FLP, which is a train of pulses that occur approximately every 16ms.
units.folder101.com/.../pulses.gif
5.b. if no FLP are seen on channel A, measure pair TD_P_D/TD_M_D. If pulses are seen, then the PHY is in mirror mode. The straight connection on the schematic is NOT mirror mode compatible.
6. Once all HW steps are verified, try connecting to a known good link partner
6.a. link partner should also be transmitting FLPs as measured in step 5.
6.b. link partner should meet IEEE TX jitter requirements
6.c. link partner should be in auto-mdix mode IF the DP83867's auto-mdix is disabled
7. if link fails, read register 0x5 and 0xa
7.a. 0x5 shows any advertised modes from the link partner, if this register is = 0x0, like above, the DP83867 and link partner are not communicating OR the link partner has disabled 10/100 modes
7.b. Register 0xA bit10 and bit11 shows the link partners advertised 1000M capability. In this case, there is nothing.

Best Regards,