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SN65DSI83: distorted test pattern & DSI data

Saiyam Doshi
Prodigy 40 points
Part Number: SN65DSI83
Other Parts Discussed in Thread: DSI-TUNER

Hello,

We are using SN65DSI83 bridge chip with our application processor to convert 4 lane MIPI DSI data to 4 lane LVDS data. Below is our configuration.

DSI:

4 data lane + 1 clock lane

DSI clock - 683 MHz  342 MHz 

LVDS:

Pixel clock - 113 MHz

Refresh rate - 50Hz

Resolution (WxH) - 1920*1080

H-front-porch- 10

H-back-porch - 70

H-sync-pulse-width - 10

V-front-porch - 10

V-back-porch - 30

V-sync-pulse-width - 10

Bits/Pixel - 24bit/RGB

Ref clock - DSI continuous clock

We have tried generated test pattern but it's distorted and flickering. Also, a portion of the test pattern is greyed out and overlapped.

Queries/Observations:

1. SN65DSI83 will be able to support this resolution? As per SN65DSI83 datasheet, it can support up to 1920x1080@60fps.

2. What should be configured for the correct test pattern?

3. After applying the attached test pattern configuration -  register 0xE5 is set to 0xC1, indicating sync/CRC error? What's the root cause for this?

4. We are able to get the data from DSI and display it on the LVDS, but same way - it's overlapped and a portion of the display is greyed out.

Please provide your input.

Thanks.

  • 0
    TI__Mastermind 35130 points
    Hi Saiyam,

    Your DSI clock frequency is significantly out of specification. The maximum DSI clock frequency for this device is 500Mhz.

    Please also go through the below links in detail for how to configure this device:
    www.youtube.com/watch
    www.youtube.com/watch
    www.ti.com/.../slla356.pdf

    Regards,
    I.K.
  • 0 in reply to Ikechukwu Anyiam
    Prodigy 40 points

    Hello I.K.,

    It's theoretically calculated value and when we configure the parameters with DSI Tuner, we are getting clock around ~340 MHz.

    We captured the DSI and LVDS clock as attached. And the DSI clock is well within the range. So consider the DSI clock as ~340 MHz.

    Also please check the attached Test pattern configuration, we are using DSI clk as a reference input for the test pattern. And the DSI clk and LVDS clk divider set accordingly.

    DSI CLK:

    LVDS CLK:

    Let us know what are we missing here?

    Thanks.

  • 0 in reply to Saiyam Doshi
    TI__Mastermind 35130 points
    Hi Saiyam,

    What video format does your panel accept? JEIDA or VESA? Please share the panel datasheet.

    And again, please go through the links I shared in detail as we will just end up going through the same debug steps regardless.

    Regards,
    I.K.
  • 0 in reply to Ikechukwu Anyiam
    Prodigy 40 points
    Hello I.K.,

    Our panel supports VESA standard. And can you please let me know what information you would need from datasheet? I will provide it.
    Can you also help me understand that, is it due to DSI clock related issue? As per the spec, SN65DSI83 will support the resolution and datarate that we are using.

    Thanks.
  • 0 in reply to Saiyam Doshi
    TI__Mastermind 35130 points
    Hi Saiyam,

    It may or may not be DSI clock related. The datarate and resolution are fine, yes, but there could also be a line time mismatch between the DSI side and the LVDS side (which is described in the resources I shared above).

    There are a couple of things I'd like to verify with the panel datasheet. For example, the pixel format, the channel mapping, the pulse polarity, the timing parameters, etc. It also looks like your reversing the order of the LVDS lanes in your script. Is that something you have to do?

    So if you can, please share the panel datasheet and your schematic with me at i-anyiam@ti.com if you don't want to post it on this forum. I can probably then use the DSI-Tuner to share settings you can use to configure the DSI83.

    Regards,
    I.K.
  • 0 in reply to Ikechukwu Anyiam
    Prodigy 40 points
    Hello I.K.

    Thank you for the information. I have shared you the datasheet and other panel related information at your mail id.

    Thanks.
  • 0 in reply to Saiyam Doshi
    TI__Mastermind 35130 points
    Closing thread as issue was resolved over email. Saiyam, if you get the chance please update this thread with the root cause and solution for future reference.

    Regards,
    I.K.