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TMDS181: about TMDS181 working mode

Vera Mao
Expert 5065 points
Part Number: TMDS181

hi dear supporting team,

customer is using TMDS181 for HDMI input, the video source is 4kP30 HDMI signal, the data rate is 3.94G, clk rate is 297M.  they found when the cable length is shorter than 1.5m, it is ok. while when it is 2.8m, then the FPGA IP core follow the TMDS181 will not recognize the video source.  and if change TMDS181 mode to redrive mode will be better than retimer mode.

they also test FPGA evk without 181 on it with the same cable lengther, the EQ used is from FPGA.  the result is very stable.

so what's the possible problem?  ( is the additive jitter of 181 cause the issue? ) thanks a lot!

  • 0
    TI__Guru**** 166411 points

    Vera

    Are they toggling HPD when switching from 1.5m to 2.8m? Can they also read TMDS_CLOCK_RATIO_STATUS bit?

    Thanks
    David

  • 0 in reply to David (ASIC) Liu
    TI__Expert 5065 points
    Hi David,
    thank you for the reply!
    yes, when switch the cable from 1.5m to 2.8m, HPD will toggle. and the TMDS_CLOCK_RATIO_STATUS bit is read as 0.
  • 0 in reply to Vera Mao
    TI__Guru**** 166411 points
    Vera

    Would you please dump both Page 0 and Page 1 register?

    Page 0 is included in the TMDS181 datasheet.

    To access Page 1, please write 0x01 to register 0xFFh, and dump register 0x00h to 0xB1.

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    TI__Expert 5065 points

    Hi David,

    thank you very much!

    below is the reg dump:

  • 0 in reply to Vera Mao
    TI__Guru**** 166411 points
    Vera

    I see TMDS181 PLL is locked, and lock is complete, so TMDS181 is in retimer mode.

    For HDMI1.4b a transmitter termination of 150 Ω to 300 Ω is allowed for data rates above 2 Gbps to compensate for reflections. The automatic termination selection will configure the TMDS181 for this. It is important to note that there are times that this is not the best solution and no termination may be needed to pass compliance. For HDMI2.0a the 75 Ω to 150 Ω transmitter termination is required and the link will not work if this is not set. Currently in I2C, the termination is set to no termination, can you please change the termination and see if it improves the performance?

    Can you also measure the TMDS181 output between redriver and retimer mode? For retimer mode, can you also reduce the EQ of the FPGA to see if it helps?

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    TI__Expert 5065 points

    Hi David,

    thank you for the reply!

    I am asking customer doing those experiment, BTW, which reg could be used to judge the working mode of 181? (i.e. whether it is Retimer or redriver mode). tks a lot!

  • 0 in reply to Vera Mao
    TI__Guru**** 166411 points
    Vera

    In redriver mode, the CDR and PLL are turned off. So by looking at the PLL_LOCK bit, we can tell whether we are in redriver or retimer mode. The fact that the register dump shows PLL in lock tells me that we are in retimer mode.

    Thanks
    David