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Original question:

DP83867E: RJ-45 Connector supported by DP83867ergz Phy

DP83867CS: Performance and RJ-45 connectors with tied transformer middles.

Eryk Druszkiewicz
Prodigy 70 points
Part Number: DP83867CS
Other Parts Discussed in Thread: AM3358

Good day,

In one of the hardware designs I have been working with, the DA1T002I3 (link) stacked RJ45 connector with magnetics is being used. In the process of the design evolution earlier this year, the DP83867CS has been put in place of an older Marvel chip (that originally called for the magnetics configuration of the DA1T002I3).

The combo of AM3358 + DP83867CS  + DA1T002I3 seems has been working pretty good, with the following two observations which we are trying explain:

1) The iperf measurements consistently show 308 Mbps TX and 421 Mbps RX, but the earlier design AM3358 + Marvell+ DA1T002I3 obtained 365 Mbps TX and 428 Mbps RX.

2) When the design with DP83867CS is connected to a Netgear GS750E switch the TX rate is as above, but the RX rate drops to 370 Mbps and ethtool reports some RX CRC Errors (less than a dozen per 1 GB received), Align/Code Errors (~20 per 1GB received), RX Jabbers (~50-100 per 1 GB received). Probing with the scope I can see that the RX_CTRL toggles unexpectedly. 

When a GS108 switch is placed in-line between the DP83867CS and GS750E (or just GS108 is used) the RX rate goes back up to 421 Mbps and no errors/jabbers are reported by ethtool. Also, RX_CTRL does not toggle unexpectedly.

And today I just came upon this thread from last month: "DP83867E: RJ-45 Connector supported by DP83867ergz Phy" which points out that the using magnetics with individual transformer middle taps is critical to DP83867 PHYs. 

Since the magnetics in the DA1T002I3 have all the transformer middles tied together:

1) Can this in the long term damage the DP83867CS or is it impacting only signal integrity?

2) Can this explain the reduced performance and sensitivity to the network switches?  

If a connector change is absolutely needed, connectors such as this one 0845-2R1T-E4 should work?

Thank you for your time and help.

  • 0
    TI__Mastermind 19780 points
    Hi Eryk,

    Throughput is effected by multiple items:
    1. Packet size
    2. inter-packet gap
    3. CPU resources
    4. Bit error rate, especially when using a protocol like TCP/IP
    5. Overhead when using extended Ethernet frame headers like VLAN

    If you are attempting a relative benchmark of performance between 2 PHYs, using the same measurement method, on the same processor, on the same network is preferred as it will control the variables of packet size, IPG, overhead, and CPU resources.

    This leaves us with looking at bit error rate between 2 PHYs. This can be impacted by different link partners as TX jitter is likely to be different from the designs, as well as the s-parameters of the channels. It looks like you have determined there is a difference and the difference is possibly related to the front end of the DP83867, as you're seeing RX errors in the form of CRC errors and align code errors.

    So, to answer your questions:
    1. Shorted center taps is an issue of signal integrity only, and not a reliability issue. Your DP83867 design will not be negatively impacted in a reliability concern.
    2. Yes, it could negatively impact the performance of the 867. You may also see sensitivity to different network switches(link partners) if the reference clock to the DP83867 is outside of the +/-100ppm, or has high jitter. If you are providing the reference from a crystal, the jitter is not likely the issue unless the Vpk-pk swing of the crystal is low, as in below 1.2Vpk-pk.

    Can you provide a schematic capture of the reference clock being supplied to the DP83867?

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 70 points

    Hello Rob,

    Thank you very much for your reply.

    The clocking source for the DP83867 in our design is done like this:

    image.png

    This is exactly the same as we did for the previous (Marvel) PHY.

    The CTX984CT-ND (625M3I025M00000) is quoted to have a frequency stability of ±50ppm.

    Does the above look acceptable to you?

    Thank you for your time and help.

     

  • 0 in reply to Eryk Druszkiewicz
    TI__Mastermind 19780 points
    Hi Eryk,

    For some reason the image did not come through. Can you add the image as an attachment?

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 70 points

    Hello Rob,

    Sure thing. Should be attached.

    I can see it still inserts it as an inline figure, so just in case I am attaching it also as a ZIP file.

    Thank you.

    DP83867ClockSource.zip

  • 0 in reply to Eryk Druszkiewicz
    TI__Mastermind 19780 points
    Hi Eryk,

    Thank you. I don't see an issue with your reference clock circuit. I believe any impact you might be seeing on signal integrity will be related to the shorted center taps for the magnetics.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 70 points
    Hello Rob,

    Thank you for looking it over and for your feedback.

    In future revisions/designs we will make sure to use the seperatelly tapped magnetics with this PHY, but for now we are glad to hear that we can keep using the current magnetics with no worry of causing damage to the PHY.

    With regards,
    Eryk D