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DS90UB954-Q1: DS90UB954 get wrong image size from DS90UB913

setphenzhou18
Prodigy 120 points
Part Number: DS90UB954-Q1
Other Parts Discussed in Thread: DS90UB913Q-Q1, DS90UB913A-Q1

Hi,I have a problem with DS90UB954,DS90UB913.The size of image is wrong.
Our circuit as follows:
IMX291 ---> DS90UB913 ---> DS90UB954 ---> Qualcomm CPU

IMX291:Parallel CMOS output, 10bit, 1945x1097, Full HD 1080p, 30fps, 74.25Mpixel/s

DS90UB913 Registers Dump:
Reg[0x00]:0xb0 Reg[0x01]:0x30 Reg[0x02]:0x20 Reg[0x03]:0xc7 Reg[0x04]:0x80 Reg[0x05]:0x14 Reg[0x06]:0xd1 Reg[0x07]:0x00 Reg[0x08]:0xd0
Reg[0x09]:0xd0 Reg[0x0a]:0x02 Reg[0x0b]:0x00 Reg[0x0c]:0x17 Reg[0x0d]:0x55 Reg[0x0e]:0x35 Reg[0x0f]:0x18 Reg[0x10]:0x17
Reg[0x11]:0x65 Reg[0x12]:0x65 Reg[0x13]:0x00 Reg[0x14]:0x00 Reg[0x1e]:0xfe Reg[0x2a]:0x00 Reg[0x2d]:0x00 Reg[0x35]:0x00

DS90UB954's regs as follows:
DS90UB954 Registers Dump:
Reg[0x00]:0x60 Reg[0x01]:0x00 Reg[0x02]:0x1e Reg[0x03]:0x20 Reg[0x04]:0xdf Reg[0x05]:0x01 Reg[0x06]:0x00 Reg[0x07]:0xfe Reg[0x08]:0x1e
Reg[0x09]:0x1c Reg[0x0a]:0x78 Reg[0x0b]:0x78 Reg[0x0c]:0x81 Reg[0x0d]:0x09 Reg[0x0e]:0x01 Reg[0x0f]:0x01 Reg[0x10]:0x00
Reg[0x11]:0x13 Reg[0x12]:0x13 Reg[0x13]:0x81 Reg[0x14]:0x13 Reg[0x15]:0x13 Reg[0x16]:0x13 Reg[0x17]:0x00 Reg[0x18]:0x00
Reg[0x19]:0x00 Reg[0x1a]:0x00 Reg[0x1b]:0x00 Reg[0x1c]:0x00 Reg[0x1d]:0x00 Reg[0x1e]:0x04 Reg[0x1f]:0x03 Reg[0x20]:0x20
Reg[0x21]:0x01 Reg[0x22]:0x00 Reg[0x23]:0x00 Reg[0x24]:0x00 Reg[0x25]:0x00 Reg[0x26]:0x00 Reg[0x27]:0x00 Reg[0x28]:0x00
Reg[0x29]:0x00 Reg[0x2a]:0x00 Reg[0x2b]:0x00 Reg[0x2c]:0x00 Reg[0x2d]:0x00 Reg[0x33]:0x01 Reg[0x34]:0x40 Reg[0x35]:0x01
Reg[0x36]:0x00 Reg[0x37]:0x01 Reg[0x39]:0x00 Reg[0x3a]:0x00 Reg[0x41]:0xa7 Reg[0x42]:0x71 Reg[0x43]:0x01 Reg[0x4a]:0x10
Reg[0x4b]:0x12 Reg[0x4c]:0x01 Reg[0x4d]:0x13 Reg[0x4e]:0x45 Reg[0x4f]:0x25 Reg[0x50]:0x20 Reg[0x51]:0x00 Reg[0x52]:0x00
Reg[0x53]:0x00 Reg[0x54]:0x00 Reg[0x55]:0x00 Reg[0x56]:0x00 Reg[0x57]:0x00 Reg[0x58]:0x58 Reg[0x59]:0x00 Reg[0x52]:0x00
Reg[0x53]:0x00 Reg[0x54]:0x00 Reg[0x55]:0x00 Reg[0x56]:0x00 Reg[0x57]:0x00 Reg[0x58]:0x58 Reg[0x59]:0x00 Reg[0x5a]:0x00
Reg[0x5b]:0xb0 Reg[0x5c]:0xb0 Reg[0x5d]:0x34 Reg[0x5e]:0x00 Reg[0x5f]:0x00 Reg[0x60]:0x00 Reg[0x61]:0x00 Reg[0x62]:0x00
Reg[0x63]:0x00 Reg[0x64]:0x00 Reg[0x65]:0x34 Reg[0x66]:0x00 Reg[0x67]:0x00 Reg[0x68]:0x00 Reg[0x69]:0x00 Reg[0x6a]:0x00
Reg[0x6b]:0x00 Reg[0x6c]:0x00 Reg[0x6d]:0x7f Reg[0x6e]:0x80 Reg[0x6f]:0x88 Reg[0x70]:0x2b Reg[0x71]:0x2c Reg[0x72]:0xe4
Reg[0x73]:0x02 Reg[0x74]:0x32 Reg[0x75]:0x0a Reg[0x76]:0xb4 Reg[0x77]:0xc5 Reg[0x78]:0x00 Reg[0x79]:0x01 Reg[0x7a]:0x00
Reg[0x7b]:0x00 Reg[0x7c]:0x20 Reg[0x7d]:0x00 Reg[0x7e]:0x00 Reg[0x7f]:0x00 Reg[0xa5]:0x18 Reg[0xb0]:0x02 Reg[0xb1]:0x49
Reg[0xb2]:0x00 Reg[0xb3]:0x08 Reg[0xb8]:0x8f Reg[0xb9]:0x33 Reg[0xba]:0x83 Reg[0xbc]:0x80 Reg[0xbe]:0x00 Reg[0xd0]:0x00
Reg[0xd2]:0x94 Reg[0xd3]:0x03 Reg[0xd4]:0x60 Reg[0xd5]:0xf2 Reg[0xd8]:0x00 Reg[0xd9]:0x00 Reg[0xda]:0x00 Reg[0xdb]:0x00
Reg[0xdc]:0x00 Reg[0xdd]:0x00 Reg[0xde]:0x00 Reg[0xdf]:0x00 Reg[0xf0]:0x5f Reg[0xf1]:0x55 Reg[0xf2]:0x42 Reg[0xf3]:0x39
Reg[0xf4]:0x35 Reg[0xf5]:0x34 Reg[0xf8]:0x00 Reg[0xf9]:0x00

However the CPU linux kernel log show as follows:
[ 69.514155] ispif_process_irq: PIX0 frame id: 0
[ 69.547509] ispif_process_irq: PIX0 frame id: 1
[ 69.580837] ispif_process_irq: PIX0 frame id: 2
[ 69.580894] msm_isp_process_overflow_irq: vfe 1 overflowmask 10,bus_error 3f9f
[ 69.584186] msm_vfe47_axi_halt: VFE1 halt for recovery, blocking 0
[ 69.591502] overflow processed
[ 69.629538] msm_isp_axi_halt: VFE1 Bus overflow detected: start recovery!
[ 69.647575] msm_vfe47_axi_halt: VFE1 halt for recovery, blocking 1
[ 69.714162] ispif_process_irq: PIX0 frame id: 3
[ 69.747542] ispif_process_irq: PIX0 frame id: 4
[ 69.747636] msm_isp_process_overflow_irq: vfe 1 overflowmask 10,bus_error 3f9f
[ 69.750957] msm_vfe47_axi_halt: VFE1 halt for recovery, blocking 0
[ 69.758259] overflow processed
[ 72.052223] msm_private_ioctl:Notifying subdevs about potential sof freeze
[ 72.052397] msm_csiphy_irq CSIPHY0_IRQ_STATUS_ADDR0 = 0x0
[ 72.058063] msm_csiphy_irq CSIPHY0_IRQ_STATUS_ADDR1 = 0x1
[ 72.063528] msm_csiphy_irq CSIPHY0_IRQ_STATUS_ADDR2 = 0x0
[ 72.068912] msm_csiphy_irq CSIPHY0_IRQ_STATUS_ADDR3 = 0x20
[ 72.074288] msm_csiphy_irq CSIPHY0_IRQ_STATUS_ADDR4 = 0x0
[ 72.079667] msm_csiphy_irq CSIPHY0_IRQ_STATUS_ADDR5 = 0x0
[ 72.080922] ispif_process_irq: PIX0 frame id: 74
[ 72.090512] msm_csiphy_irq CSIPHY0_IRQ_STATUS_ADDR6 = 0x4
[ 72.095207] msm_csiphy_irq CSIPHY0_IRQ_STATUS_ADDR7 = 0x0
[ 72.100500] msm_csiphy_irq CSIPHY0_IRQ_STATUS_ADDR8 = 0x80
[ 72.105885] msm_csiphy_irq CSIPHY0_IRQ_STATUS_ADDR9 = 0x40
[ 72.111752] msm_csid_irq CSID0_IRQ_STATUS_ADDR = 0xff

we find DS90UB954 get image size (reg 0x73-0x76) is WRONG!!!!
Can you help me to slove this problem?

  • 0
    TI__Expert 3055 points
    Hello Stephen,

    Are you using the 913 or the 913A?

    There are some timing requirements when operating the 954 in DVP mode.

    Based on your registers settings, the FV_MIN_TIME is set to the default value of 128. When operating in RAW10 mode, this means that there must be a delay of 261 PCLK cycles between the initial FV and the initial LV (in your case, this would be 3.52 us). Can you check that this is the case?

    Also, can you share what the inactive period is in between each LV signal?

    Please try running the internal pattern generator on the 913 and see if you also have errors in that case. This will help rule out other configuration issues.

    Regards,

    Zoe
  • 0 in reply to Zoe Nuyens
    Prodigy 120 points

    Yes, we use DS90UB913Q-Q1 with DS90UB954TRGZRQ1.

    As the 954 doc shows, I have set the CSI2 400Mbps timing regs.

    After reading your suggestion, I  set  the FV_MIN_TIME  (reg 0xbc) of 954 to value  0x0, 0x10, 0x40. But all take no effect.

    The size (0x73-0x76) always Reg[0x73]:0x02  Reg[0x74]:0x32  Reg[0x75]:0x0a  Reg[0x76]:0xb4.

    I can't understand " the inactive period is in between each LV signal",  so I paste the snap picture from the IMX291 specification.

    In our previous design, we use 913 with 914,  they work ok. So we just replace 914 with 954, and not change the 913  and the imx291 configuration. 

    Could you give me some advice about this problem?

  • 0 in reply to setphenzhou18
    TI__Expert 3055 points

    Hi Stephen,

    Can you share a block diagram of the system with me? Registers 0x73-0x76 are only accurate for a single video stream; are you using both input ports on the 954?

    Can you please measure at the input to the 913 what the time is between the frame valid and line valid and in between assertions of line valid? See the diagram below.

    Regards,

    Zoe

  • 0 in reply to Zoe Nuyens
    Prodigy 120 points

    Hi  Zoe,

    Our system diagram is shown as follows.

    We can't find the FV, LV in our circuit. So we measure the XVS, XHS, you can find them in 913, then we get Tfv_lv is 29us, Tlv_lv is 30us.

  • 0 in reply to setphenzhou18
    TI__Expert 3055 points
    Hi Stephen,

    Thanks for sharing the block diagram. One note, It is recommended to use the DS90UB913A-Q1, not the 913 for coax applications.

    That timing should be ok. Can you also measure this timing at the 954 to confirm? FV and LV can be output on the 954 GPIOs for measurement. Please share the picture of the waveforms.

    As well, are you able to view the image on a display? If possible, can you display the image from the output of the deserializer and also display the image directly from the imager?

    Can you also confirm that the devices are consistently locked (that lock is not intermittent)? I noticed that register 0x4D on the 954 has the lock_sts_chg bit checked.

    Regards,
    Zoe
  • 0 in reply to Zoe Nuyens
    Prodigy 120 points

    Hi Zoe,

    Thanks for your suggestion. I have found the 913 chip on the circuit board. We actually use DS90UB913A-Q1.

    I measure the 913 XHS,XVS again.  Tfv_lv is 100ns, Tlv_lv on 954 gpio is 29.30us.

    I have measure the FV and LV on the 954 GPIOs. Tfv_lv is 82ns, Tlv_lv on 954 gpio is 29.64us.

    I have tried to get the image from qualcomm CPU, but all fail. Sorry.

    Before starting the sensor to capture, I read 0x4D to clear the lock status change bit. Then I start the camera, the lock_sts_chg bit always 0.

    Regards,

    Stephen

  • 0 in reply to setphenzhou18
    TI__Expert 3055 points
    Hi Stephen,

    I assume you are using FV_MIN_TIME of 0x0. As long as your FV_MIN_TIME is 0x02 or less, this timing should be fine.

    Can you double check your imager configuration?

    Regards,
    Zoe
  • 0 in reply to Zoe Nuyens
    Prodigy 120 points
    Hi Zoe,

    We use 913 and 914 previously, the imager is imx291. Now we only replace 914 with 954, and others are not changed.
    We use the same configuration. After checking the configuration, I think the imager's configuration should be ok.

    Regards,
    Stephen
  • 0 in reply to setphenzhou18
    TI__Expert 3055 points
    Hi Stephen,

    Just to confirm, can you send me the updated register dump for the 954 after changing FV_MIN_TIME?

    Also, can you read 0x73-0x76 multiple times in a row and let me know what the values are?

    Regards,
    Zoe
  • 0 in reply to Zoe Nuyens
    Prodigy 120 points
    Hi Zoe,

    I have change the value, but it does'n work. I find the RX_FREQ_LOW changed.
    First time,
    DS90UB954 Registers Dump:
    Reg[0x00]:0x60 Reg[0x01]:0x00 Reg[0x02]:0x1e Reg[0x03]:0x20 Reg[0x04]:0xdf Reg[0x05]:0x01 Reg[0x06]:0x00 Reg[0x07]:0xfe
    Reg[0x08]:0x1e Reg[0x09]:0x1c Reg[0x0a]:0x78 Reg[0x0b]:0x78 Reg[0x0c]:0x81 Reg[0x0d]:0x09 Reg[0x0e]:0x00 Reg[0x0f]:0x01
    Reg[0x10]:0x00 Reg[0x11]:0x13 Reg[0x12]:0x13 Reg[0x13]:0x81 Reg[0x14]:0x13 Reg[0x15]:0x13 Reg[0x16]:0x13 Reg[0x17]:0x00
    Reg[0x18]:0x00 Reg[0x19]:0x00 Reg[0x1a]:0x00 Reg[0x1b]:0x00 Reg[0x1c]:0x00 Reg[0x1d]:0x00 Reg[0x1e]:0x04 Reg[0x1f]:0x03
    Reg[0x20]:0x20 Reg[0x21]:0x01 Reg[0x22]:0x00 Reg[0x23]:0x00 Reg[0x24]:0x00 Reg[0x25]:0x00 Reg[0x26]:0x00 Reg[0x27]:0x00
    Reg[0x28]:0x00 Reg[0x29]:0x00 Reg[0x2a]:0x00 Reg[0x2b]:0x00 Reg[0x2c]:0x00 Reg[0x2d]:0x00 Reg[0x33]:0x01 Reg[0x34]:0x40
    Reg[0x35]:0x00 Reg[0x36]:0x00 Reg[0x37]:0x03 Reg[0x39]:0x00 Reg[0x3a]:0x00 Reg[0x41]:0xa9 Reg[0x42]:0x71 Reg[0x43]:0x01
    Reg[0x4a]:0x10 Reg[0x4b]:0x52 Reg[0x4c]:0x01 Reg[0x4d]:0x13 Reg[0x4e]:0x45 Reg[0x4f]:0x18 Reg[0x50]:0xad Reg[0x51]:0x00
    Reg[0x52]:0x00 Reg[0x53]:0x00 Reg[0x54]:0x00 Reg[0x55]:0x00 Reg[0x56]:0x00 Reg[0x57]:0x00 Reg[0x58]:0x58 Reg[0x59]:0x00
    Reg[0x5a]:0x00 Reg[0x5b]:0xb0 Reg[0x5c]:0xb0 Reg[0x5d]:0x34 Reg[0x5e]:0x00 Reg[0x5f]:0x00 Reg[0x60]:0x00 Reg[0x61]:0x00
    Reg[0x62]:0x00 Reg[0x63]:0x00 Reg[0x64]:0x00 Reg[0x65]:0x34 Reg[0x66]:0x00 Reg[0x67]:0x00 Reg[0x68]:0x00 Reg[0x69]:0x00
    Reg[0x6a]:0x00 Reg[0x6b]:0x00 Reg[0x6c]:0x00 Reg[0x6d]:0x7b Reg[0x6e]:0x80 Reg[0x6f]:0x88 Reg[0x70]:0x2b Reg[0x71]:0x2c
    Reg[0x72]:0xe4 Reg[0x73]:0x02 Reg[0x74]:0x32 Reg[0x75]:0x0a Reg[0x76]:0xb4 Reg[0x77]:0xc5 Reg[0x78]:0x00 Reg[0x79]:0x01
    Reg[0x7a]:0x00 Reg[0x7b]:0x00 Reg[0x7c]:0x20 Reg[0x7d]:0x00 Reg[0x7e]:0x00 Reg[0x7f]:0x00 Reg[0xa5]:0x18 Reg[0xb0]:0x02
    Reg[0xb1]:0x4d Reg[0xb2]:0x00 Reg[0xb3]:0x08 Reg[0xb8]:0x8f Reg[0xb9]:0x33 Reg[0xba]:0x83 Reg[0xbc]:0x00 Reg[0xbe]:0x00
    Reg[0xd0]:0x00 Reg[0xd2]:0x94 Reg[0xd3]:0x0f Reg[0xd4]:0x60 Reg[0xd5]:0xf2 Reg[0xd8]:0x00 Reg[0xd9]:0x00 Reg[0xda]:0x00
    Reg[0xdb]:0x00 Reg[0xdc]:0x00 Reg[0xdd]:0x00 Reg[0xde]:0x00 Reg[0xdf]:0x00 Reg[0xf0]:0x5f Reg[0xf1]:0x55 Reg[0xf2]:0x42
    Reg[0xf3]:0x39 Reg[0xf4]:0x35 Reg[0xf5]:0x34 Reg[0xf8]:0x00 Reg[0xf9]:0x00

    DS90UB913 Registers Dump:
    Reg[0x00]:0xb0 Reg[0x01]:0x30 Reg[0x02]:0x20 Reg[0x03]:0xc7 Reg[0x04]:0x80 Reg[0x05]:0x14 Reg[0x06]:0xb1 Reg[0x07]:0x00 Reg[0x08]:0xb0
    Reg[0x09]:0xb0 Reg[0x0a]:0x04 Reg[0x0b]:0x00 Reg[0x0c]:0x13 Reg[0x0d]:0x55 Reg[0x0e]:0x35 Reg[0x0f]:0x18 Reg[0x10]:0x17
    Reg[0x11]:0x65 Reg[0x12]:0x65 Reg[0x13]:0x00 Reg[0x14]:0x00 Reg[0x1e]:0xfe Reg[0x2a]:0x00 Reg[0x2d]:0x00 Reg[0x35]:0x00



    Try open camera again,
    DS90UB954 Registers Dump:
    Reg[0x00]:0x60 Reg[0x01]:0x00 Reg[0x02]:0x1e Reg[0x03]:0x20 Reg[0x04]:0xdf Reg[0x05]:0x01 Reg[0x06]:0x00 Reg[0x07]:0xfe
    Reg[0x08]:0x1e Reg[0x09]:0x1c Reg[0x0a]:0x78 Reg[0x0b]:0x78 Reg[0x0c]:0x81 Reg[0x0d]:0x09 Reg[0x0e]:0x00 Reg[0x0f]:0x01
    Reg[0x10]:0x00 Reg[0x11]:0x13 Reg[0x12]:0x13 Reg[0x13]:0x81 Reg[0x14]:0x13 Reg[0x15]:0x13 Reg[0x16]:0x13 Reg[0x17]:0x00
    Reg[0x18]:0x00 Reg[0x19]:0x00 Reg[0x1a]:0x00 Reg[0x1b]:0x00 Reg[0x1c]:0x00 Reg[0x1d]:0x00 Reg[0x1e]:0x04 Reg[0x1f]:0x03
    Reg[0x20]:0x20 Reg[0x21]:0x01 Reg[0x22]:0x00 Reg[0x23]:0x00 Reg[0x24]:0x00 Reg[0x25]:0x00 Reg[0x26]:0x00 Reg[0x27]:0x00
    Reg[0x28]:0x00 Reg[0x29]:0x00 Reg[0x2a]:0x00 Reg[0x2b]:0x00 Reg[0x2c]:0x00 Reg[0x2d]:0x00 Reg[0x33]:0x01 Reg[0x34]:0x40
    Reg[0x35]:0x00 Reg[0x36]:0x00 Reg[0x37]:0x03 Reg[0x39]:0x00 Reg[0x3a]:0x00 Reg[0x41]:0xa9 Reg[0x42]:0x71 Reg[0x43]:0x01
    Reg[0x4a]:0x10 Reg[0x4b]:0x52 Reg[0x4c]:0x01 Reg[0x4d]:0x13 Reg[0x4e]:0x45 Reg[0x4f]:0x18 Reg[0x50]:0xaa Reg[0x51]:0x00
    Reg[0x52]:0x00 Reg[0x53]:0x00 Reg[0x54]:0x00 Reg[0x55]:0x00 Reg[0x56]:0x00 Reg[0x57]:0x00 Reg[0x58]:0x58 Reg[0x59]:0x00
    Reg[0x5a]:0x00 Reg[0x5b]:0xb0 Reg[0x5c]:0xb0 Reg[0x5d]:0x34 Reg[0x5e]:0x00 Reg[0x5f]:0x00 Reg[0x60]:0x00 Reg[0x61]:0x00
    Reg[0x62]:0x00 Reg[0x63]:0x00 Reg[0x64]:0x00 Reg[0x65]:0x34 Reg[0x66]:0x00 Reg[0x67]:0x00 Reg[0x68]:0x00 Reg[0x69]:0x00
    Reg[0x6a]:0x00 Reg[0x6b]:0x00 Reg[0x6c]:0x00 Reg[0x6d]:0x7b Reg[0x6e]:0x80 Reg[0x6f]:0x88 Reg[0x70]:0x2b Reg[0x71]:0x2c
    Reg[0x72]:0xe4 Reg[0x73]:0x02 Reg[0x74]:0x32 Reg[0x75]:0x0a Reg[0x76]:0xb4 Reg[0x77]:0xc5 Reg[0x78]:0x00 Reg[0x79]:0x01
    Reg[0x7a]:0x00 Reg[0x7b]:0x00 Reg[0x7c]:0x20 Reg[0x7d]:0x00 Reg[0x7e]:0x00 Reg[0x7f]:0x00 Reg[0xa5]:0x18 Reg[0xb0]:0x02
    Reg[0xb1]:0x4e Reg[0xb2]:0x00 Reg[0xb3]:0x08 Reg[0xb8]:0x8f Reg[0xb9]:0x33 Reg[0xba]:0x83 Reg[0xbc]:0x00 Reg[0xbe]:0x00
    Reg[0xd0]:0x00 Reg[0xd2]:0x94 Reg[0xd3]:0x1f Reg[0xd4]:0x60 Reg[0xd5]:0xf2 Reg[0xd8]:0x00 Reg[0xd9]:0x00 Reg[0xda]:0x00
    Reg[0xdb]:0x00 Reg[0xdc]:0x00 Reg[0xdd]:0x00 Reg[0xde]:0x00 Reg[0xdf]:0x00 Reg[0xf0]:0x5f Reg[0xf1]:0x55 Reg[0xf2]:0x42
    Reg[0xf3]:0x39 Reg[0xf4]:0x35 Reg[0xf5]:0x34 Reg[0xf8]:0x00 Reg[0xf9]:0x00

    DS90UB913 Registers Dump:
    Reg[0x00]:0xb0 Reg[0x01]:0x30 Reg[0x02]:0x20 Reg[0x03]:0xc7 Reg[0x04]:0x80 Reg[0x05]:0x14 Reg[0x06]:0xb1 Reg[0x07]:0x00 Reg[0x08]:0xb0
    Reg[0x09]:0xb0 Reg[0x0a]:0x04 Reg[0x0b]:0x00 Reg[0x0c]:0x13 Reg[0x0d]:0x55 Reg[0x0e]:0x35 Reg[0x0f]:0x18 Reg[0x10]:0x17
    Reg[0x11]:0x65 Reg[0x12]:0x65 Reg[0x13]:0x00 Reg[0x14]:0x00 Reg[0x1e]:0xfe Reg[0x2a]:0x00 Reg[0x2d]:0x00 Reg[0x35]:0x00

    Regards,
    Stephen
  • 0 in reply to setphenzhou18
    TI__Intellectual 1930 points

    Hi Stephen,

    I noticed you are setting register 0x6D to 0x7B, where bit 2 is set to 0. This means you are running the system in STP mode. Just want to double check if that is the intended mode. If you are using coax, register should be set to 0x7F.

    In addition, have you modified the SoC from your previous setup? I'm beginning to wonder if the SoC needs to be configured. In your previous system with the 913-914, the output of the serializer was DVP so the SoC would have needed to interpret the DVP data. In this new setup you are outputting 4 lanes of CSI data. Can you verify the SoC is properly configured for this new use case?

    Thanks,

    Mostafa

  • 0 in reply to Mostafa Shuva
    Prodigy 120 points
    Hi Mostafa,

    I have checked that the system was running in STP mode,

    When we use 953 with 954, they work ok. If we just replace 953 with 913, the 954 will be operated in the DVP mode .Which different hardware port of 954 should be configured in both cases? Could you give me some advice about this problem?

    Thanks
  • 0 in reply to setphenzhou18
    TI__Intellectual 1930 points

    Hi Stephen,

    Can you please provide register dump of the following configurations:

    • 953 to 954
    • 913 to 954

    Since you indicated that everything works when you have a 953/954 connection and then the system fails when the 953 is replaced with a 913, it would be good to look at what is inside the registers.

    If I understand correctly, you did the following:

    1. Configure the 953 to work with the 954
    2. Verified the sensor and SoC were configured properly, and observed proper video frame output/size.
    3. Replace the 953 with a 913A (without modifying the sensor and SoC), and configure the 954 to backwards compatibility mode.
    4. Observe incorrect video frame output/size.

  • 0 in reply to Mostafa Shuva
    Prodigy 120 points
    953 954 CSI MODE work OK
    DS90UB953 Registers Dump:
    Reg[0x00]:0x30 Reg[0x01]:0x00 Reg[0x02]:0x33 Reg[0x03]:0x4b Reg[0x04]:0x00 Reg[0x05]:0x03 Reg[0x06]:0x41 Reg[0x07]:0x28 Reg[0x08]:0xfe
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    954, 913A DVP MODE work FAIL
    DS90UB954 Registers Dump:
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  • 0 in reply to Zoe Nuyens
    Prodigy 120 points
    953 954 CSI MODE work OK
    DS90UB953 Registers Dump:
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    DS90UB954 Registers Dump:
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    954, 913A DVP MODE work FAIL
    DS90UB954 Registers Dump:
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    DS90UB913 Registers Dump:
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  • 0 in reply to setphenzhou18
    TI__Intellectual 2935 points

    Hi, Team,

    Could you give some feedback for this? Thanks!

  • 0 in reply to Wu JW
    TI__Intellectual 1930 points

    Hi Stephen,

    Can you please confirm that your PCLK frequency is stable/not changing? Can you measure what the PCLK is on the 913A input side and the 954 output.