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LMH0397: LMH0397/12xx　SS_N deassertion timing for SPI Read operation

Shibuya
Intellectual 2985 points
Part Number: LMH0397

Hello team,

I would like to know SS_N deassertion timing requirement for LMH0397 and LMH12xx SPI Read operation.

According to datasheet and LMH12xx SPI Access video, SS_N deassertion is needed between the first 17 bit read transaction and the second dummy transaction to latch the Read identification and 8 bit address in the first transaction.

  • Can I deassert SS_N during the eight 1s ignorable address bit?  (I do not need to wait the end of the first 17 bit frame?)   : 

  • What is the timing requirement between SS_N reassertion and valid MISO data in the second transaction?

Best regards,

Tertsuro

 

  • 0
    TI__Guru* 93670 points
    Greetings Tertsuro,

    1). If we deassert SS_N during the eight !s as you noted, wrong address/data would be latched by the device. To clear this up, we need to shift in at least 17 !s or valid address and data.

    2). Valid MISO after SS_N is determined by SCK period, Tsssu, and Tod parameters. Please refer to the data sheet timing table for these parameters.

    Regards,,nasser
  • 0 in reply to Nasser Mohammadi
    TI__Intellectual 2985 points

    Hi Masser,

    If we need to satisfy Tsssu, following timing diagram in the datasheet is impossible.

    Is my understaing correct?

    In addition, following diagram (no SS_N assertion between 1st and 2nd transaction) is possible?

    Best regards,

    Tetsuro

    Correct diagram should be as follow.

  • 0 in reply to Nasser Mohammadi
    TI__Intellectual 2985 points

    Hi Masser,

    Resend the message because It seems the pictures in provious message are missing.

    If we need to satisfy Tsssu, following timing diagram in the datasheet is impossible.

    And following diagram should be correct.

    Is my understanding correct?
    In addition, is following diagram (no SS_N assertion between 1st and 2nd transaction) possible?

    Best regards,

    Tetsuro

  • 0 in reply to Shibuya
    TI__Guru* 93670 points

    Hi Tetsuro,

    Your understanding is correct and your diagram for Tsssu is correct. I will keep this in mind and we correct this in the next revision of the data sheet.

    2). As it relates to your last diagram, device MUST see SS_N de-assertion between first 17-bits and second 17-bits to decode the register number and fetch content of the register. Also, SS_N must be off for at least 1uS.

    Regards,,nasser