Linux/TLK10232: Pattern Generator / Checker Issue on LS / HS

Avinash N,

In your posted figure it shows you are using a SFP+ module. When using TLK10232 with SFP+ with Auto Negotiation and Link Training you will see errors due to incorrect setting chosen by the device. Thank you for posting how you are configuring your resisters settings. I will look over these and get back to you. In the meantime could you reply with the following details:

• Could you provide steps on how you are testing the device? Do you need guidance for creating a test when using the TLK10232 with SPF+?
• What is the specific error you are seeing when running your test?
• Are you able to establish a connection between your T4240 Processor  and  SFP+ link?

Hi Malik Barton,

1. When using TLK10232 with SFP+ with Auto Negotiation and Link Training you will see errors due to incorrect setting chosen by the device.

    In our above mentioned configuration we have disabled the auto negotiation and link training settings.

2. Could you provide steps on how you are testing the device?

Board 1    XAUI                                                  Fiber Cable                                                   XAUI      Board 2

T4240    <=====> TLK10232 <=====> SFP+ <==========> SFP+ <======> TLK10232 <======> T4240

TX port                                                                                                                                                RX port

3. Do you need guidance for creating a test when using the TLK10232 with SPF+?

     Yes

4. What is the specific error you are seeing when running your test?

   eth2 Link encap:Ethernet HWaddr xx:xx:xx:xx:xx:xx ...

  RX packets:277593775 errors:4096 dropped:0 overruns:0 frame:0

5.  Are you able to establish a connection between your T4240 Processor  and  SFP+ link?

     Yes.

Question:

1. Can you just provide some test setup to test the LS Side and HS Side using test pattern generator and tester ?

2. Can you just provide some test setup to perform the loopback test ?

Regards,

Avinash N

 

 

Avinash N,

Its seems that your setting for the below resisters are not optimal indicated by "0x1E.0x0010 - 0xFFFF". In order to find optimal settings for your system I would continue testing how you have been so far. It seems that the LS side TLK10232 is functional. To confirm read LS_LNx_ERROR_COUNTER registers. Trying different combinations of the registers below to minimize HS_ERROR_COUNTER. Make sure to write 0x03FF to 0x1E.8020. This allows the link settings that would normally be configured through KR training to be configured manually instead. This should be done for each channel. 

•  HS_SWING
•  HS_AGCCTRL
•  HS_EQPRE
• HS_ENTRACK
• HS_EQPRE
• HS_PEAK_DISABLE
• HS_H1CDRMODE

When you are testing your system, how long do you run the test for, in other words when was 0x1E.0x0010 read in your testing?  

Hi Malik Barton,

I have tested with various combinations of above mentioned parameters , But still we can't able to achieve 10G Throughput. Is there any test procedure can be done to test internal loop. We have provided 156.25 MHz clock . we have selected the serdes PLL for low speed side 10 and for high speed side 16.5 along with Rate = FULL.

Any software test setup is available to resolve this LS and HS side issue.

Any hardware or design constraints need to be followed ?

Regards,

Avinash N

Avinash N,

See below for the Loopback procedure we discussed in a previous thread on this device. Does this not work for you? Also please make sure AC coupling is located on HS and LS data lines as well as REFCLK lines. 

• Shallow local loopback mode
  • write 0x1E.0x0 0x8610
  • write 0x1E.0x001D 0x0000
  • write 0x07.0x0 0x20000
  • write 0x01.0x0096 0x0000
  • write 0x01.0x000B 0x0D11
  • write 0x1E.0x8020 0x03FF
  • write 0x1E.0x0004 0x9500
  • write 0x1E.0x0004 0xD500
  • write 0x1E.0xE 0x0008
• mdio read 0x1E.0x000F - 0x0

• Deep remote loopback mode
  • write 0x1E.0x0 0x8610
  • write 0x1E.0x001D 0x0000
  • write 0x07.0x0 0x20000
  • write 0x01.0x0096 0x0000
  • write 0x01.0x000B 0x0D18
  • write 0x1E.0x8020 0x03FF
  • write 0x1E.0x0004 0x9500
  • write 0x1E.0x0004 0xD500
  • write 0x1E.0xE 0x0008
• mdio read 0x1E.0x000F - 0x0

Hi Malik Barton,

1. Does this not work for you? 

• Shallow local loopback mode
  • write 0x1E.0x0 0x8610
  • write 0x1E.0x001D 0x0000
  • write 0x07.0x0 0x20000
  • write 0x01.0x0096 0x0000
  • write 0x01.0x000B 0x0D11
  • write 0x1E.0x8020 0x03FF
  • write 0x1E.0x0004 0x9500
  • write 0x1E.0x0004 0xD500
  • write 0x1E.0xE 0x0008
• mdio read 0x1E.0x000F - 0x5803

• Deep remote loopback mode
  • write 0x1E.0x0 0x8610
  • write 0x1E.0x001D 0x0000
  • write 0x07.0x0 0x20000
  • write 0x01.0x0096 0x0000
  • write 0x01.0x000B 0x0D18
  • write 0x1E.0x8020 0x03FF
  • write 0x1E.0x0004 0x9500
  • write 0x1E.0x0004 0xD500
  • write 0x1E.0xE 0x0008
• mdio read 0x1E.0x000F - 0x5803

2. Also please make sure AC coupling is located on HS and LS data lines as well as REFCLK lines. 

For INB[3:0]P/N & INA[3:0]P/N AC coupling capacitors are placed away from TLK10232 and OUTB[3:0]P/N & OUTA[3:0]P/N AC coupling capacitors are placed near the TLK10232. Regarding the HS signal's the AC coupling capacitors are placed placed away from TLK10232.

Regards,

Avinash N

 & Also please make sure AC coupling is located on HS and LS data lines as well as REFCLK lines. 

Avinash N,

It seems you are having underflow on the RX and TX data paths. One possibility is that the receive reference clock tolerance (ppm) or tolerance of the transmit clock on the other side may not be according to spec. If that is the case, the RX FIFO cannot compensate for the clock difference anymore and you can have underflow (or overflow). I would review "11 APPENDIX A: PROVISIONABLE XAUI CLOCK TOLERANCE COMPENSATION" and "4.3 TX CTC"  for more information. To confirm I would measure the change in frequency for REFCLK for both TLK10232 in your system and ensure it meets the FHSoffset spec in TLK10232 datasheet. Then compare the recovered byte clock from incoming data to REFCLK for each TLK10232. You may need to add additional IDLE patterns to your data or increase the FIFO size in order to increase valid data throughput. Increasing FIFO size will increase data latency through TLK10232. 

Hi,

I don't want to be unpleasant but you need to do something about TLK10232 Documentation.

1/
write 0x1E.0x8020 to 0x03FF BUT WHAT IS THE 0x1E.0x8020 REGISTER. Datasheet don't have any information about this register.

2/
write 0x1E.0x0004 0x9500
write 0x1E.0x0004 0xD500

Why you don't write only 0xD500. It's the same thing.
Documentation seem to be a mix between different model o f XAUI component.

3/
In all your post, one register is never configured : CLK_CONTROL 0x1E 0x000D
I'm am in the same configuration that you (156.25MHz for 3.125Gbps LS side and 10GB-KR in HS SIDE) and value that i used is
0x2f4f for this register.
I cannot use CLKOUT_SEL[3:0] = 00x0 (default value) or 10x0. I don't know why but when i used it i don't have clock in CLKOUTx_P/N pin.
In my case i use CLKOUT_SEL[3:0] = 1111. This configuration place the CLKOUTx_P/N pin @ 156.25MHz if you use CLKOUT_DIV[3:0] = 0100 (divide by 2).

In your case you don't configure this register so default value is used for CLKOUT_SEL[3:0] = 00x0. If you check the CLKOUTx_P/N pin with an oscilloscope you will see that frequency value is not good.

You can check with this register, and if it don't works i will try to send you all my intialization for HS side loopback.

4/
i see that your PRBSEN signal is '1'. When i configure test pattern by MDIO in loopback mode i don't use signal PRBSEN (='0').
Have you read the SLLA351 document. It's an useful document with a lot of information.

Hi Malik Barton.

Sorry for delay response. We are using the following clock in our board,

Hi Malik,

             Sorry for the delay response. In our customised board we can able to achieve only 4Gbps in TCP.  we are using Isola I - SPEED material for 10G Interface. Approximately 2 inches of trace  between TLK10232 IC and SPF+ optical module cage.

    Any constraints is there for PCB material or any other constraints need to be taken care ?

    We are facing Issue on Receiver side as per our suspect, any procedure or ideas to debug and resolve this issue ?

   Regards,

Avinash N