• State TI Thinks Resolved
  • Locked Locked
  • Replies 10 replies
  • Answers 1 answer
  • Subscribers 34 subscribers
  • Views 585 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN65DSI85: test pattern starts, runs for a bit then stops

Eric Steimle
Expert 2290 points
Part Number: SN65DSI85
Other Parts Discussed in Thread: DSI-TUNER

I have a test pattern running, it seems to be going fine for a few minutes, but then the output abruptly stops. All the registers are still set.  Any idea what could cause this?

  • 0
    TI__Mastermind 35130 points
    Hi Eric,

    Are you using the DSI CLK to generate the LVDS CLK? Is the DSI CLK continous and never stopping?

    Regards,
    I.K.
  • 0 in reply to Ikechukwu Anyiam
    Expert 2290 points
    No it's an external 74.25Mhz clock, verified to be running on the scope.

    # Set Clocks
    ./i2cset_normal_syk -f -y 12 0x2C 0x0A 0x04
    ./i2cget_syk -f -y 12 0x2C 0x0A

    # clock setup
    ./i2cset_normal_syk -f -y 12 0x2C 0x0B 0x00
  • 0 in reply to Eric Steimle
    TI__Mastermind 35130 points
    Hi Eric,

    Understood. Here are some additional questions/items to check:

    1. Is the LVDS CLK still running when the output stops?
    2. Are you configuring all the registers before setting the PLL_EN bit?
    3. Are any bits being set in error register 0xE5/0xE6? (Please clear these registers by writing 0xFF to them before reading them)
    4. Is the external reference clock within the electrical and switching characteristics of the datasheet?
    5. Are you able to try generating the test pattern by using the DSI CLK instead of an external reference clock (ensure to follow the initialization sequence in the datasheet)?
    6. Can you share your display datasheet and register settings. Sharing the settings with the DSI-Tuner would be preferable, and you can email the display datasheet to i-anyiam@ti.com if you do not want to share it on this forum.

    Regards,
    I.K.
  • 0 in reply to Ikechukwu Anyiam
    Expert 2290 points
    I will try these things. Quick question about the color bar pattern. Is it horizontal stripes of color now (color changes from top to bottom)? That's what I see when it's working, like a rainbow from top to bottom. Instead of that more traditional color bar pattern of vertical stripes (color changes from left to right). Only asking to know if my display is working.
  • 0 in reply to Eric Steimle
    TI__Mastermind 35130 points
    I believe it should be vertical bars, similar to the pattern in figure 1 of this document: www.ti.com/.../slla356.pdf

    Regards,
    I.K.
  • 0 in reply to Ikechukwu Anyiam
    Expert 2290 points

    1. Is the LVDS CLK still running when the output stops? 

    Yes 74.25Mhz, it comes from a 1.8V powered oscillator.


    2. Are you configuring all the registers before setting the PLL_EN bit?

    I wasn't but I moved it to the end of my configuration script, and same result


    3. Are any bits being set in error register 0xE5/0xE6? (Please clear these registers by writing 0xFF to them before reading them)

    Yes I cleared them with 0xFF at the start of my script 0xE6 was 0x40 0xE5 was 0x01, but it's always 0x01 even in our other production 720p systems that use the DSI83.

    Clearing these bits again, and trying a soft reset doesn't bring back the test pattern.


    4. Is the external reference clock within the electrical and switching characteristics of the datasheet?

    I believe so, it is 74.25Mhz at 1.8V.  It is the same oscillator we use in our production DSI83 based systems.


    5. Are you able to try generating the test pattern by using the DSI CLK instead of an external reference clock (ensure to follow the initialization sequence in the datasheet)? 

    No, that is supposed to happen after we prove that the DSI85 is working with the test pattern.


    6. Can you share your display datasheet and register settings. Sharing the settings with the DSI-Tuner would be preferable, and you can email the display datasheet to i-anyiam@ti.com if you do not want to share it on this forum.

    I don't think so, it's under NDA and TI could be considered a competitor with your DLP displays. 

    I can share the timing:

      lines hex     clocks hex
    lines 1080 438   active pixels 1920 780
    vsync 5 5   hsync  44 2C
    vertical back porch 36 24   back porch 148 94
    vertical front porch 4 4   front porch 88 58
    total 1125 465     2200 898

    pixel clock is 148.5MHz

  • 0 in reply to Eric Steimle
    TI__Mastermind 35130 points
    Hi Eric,

    Can you input your settings into the DSI-Tuner tool and share either the .dsi file with me or just post screenshots of the windows? The display datasheet information you shared is not enough for me to generate a configuration file for you or check if the settings you are using are correct. Please also provide a register dump.

    This video should give you an idea of what information I need from the datasheet to help you debug this issue: www.youtube.com/watch

    For the error registers 0xE5/0xE6, you should clear them at the end of your script after the initialization sequence is complete, not at the start, since some bits may be erroneously set during initialization. Are the bits in these registers still being set after the initialization sequence?

    One other thing I'll need you to confirm for me is that you are following the initialization sequence described in the datasheet. This sequence is required for correct operation of the device.

    Regards,
    I.K.
  • 0 in reply to Ikechukwu Anyiam
    Expert 2290 points

    Fullscreen ti_dsi_output.dsi.txt Download 
    %CHIP3%PVCAraon-tech%PMCARDC200%RPCA1920%RLCA1080%PVCB%PMCB%RPCB%RLCB%LVCM0%HPWA44%HBPA148%HFPA88%HACA1920%HTOA2200%HPWB%HBPB%HFPB%HACB%HTOB0%VPWA5%VBPA36%VFPA4%VACA1080%VTOA1125%VPWB%VBPB%VFPB%VACB%VTOB0%PCKN148.5%LCKS1%RCKM74.25%MULT1%DCKA%DIVI0%LCKR148.5%FMTA1%DEPA0%HSPA1%VSPA1%BPPA1%FMTB1%DEPB0%HSPB1%VSPB1%BPPB0%PRDA1920x1080%PRDBx%DSCM0%LREO1%LRCE1%LPCA0%BMCA0%SMCA0%LPCB0%BMCB0%SMCB0%DHPA44%DHBA148%DHFA88%DHAA1920%DHTA2200%DHPB%DHBB%DHFB%DHAB%DHTB%DVPA5%DVBA36%DVFA4%DVAA1080%DVTA1125%DVPB%DVBB%DVFB%DVAB%DVTB%DDRA1039.5%NOLA3%VIMA0%LCRP%DDRB%NOLB0%VIMB0%RCRP

    Here's the output from dsi tuner, I had to add the .txt extension for the website to allow me to upload it.

    Here's the output from dsi tuner

  • 0 in reply to Ikechukwu Anyiam
    Expert 2290 points
    I got it to work. I had to manually reset the TI part, then run the script. Only then will the test pattern come out all the time.

    I have a TI reset supervisor monitoring 1.8V going to the DSI85. I checked and both my external reference clock and 1.8V are up well before it comes out of reset. I'm sure DSI clock is not though.

    Why do I have to do this additional reset?

    Thank you
  • 0 in reply to Eric Steimle
    TI__Mastermind 35130 points
    Hi Eric,

    There is probably something amiss with your initialization sequence. For example, the DSI CLK needs to be in HS before EN is asserted. Please ensure to implement the initialization sequence as described in the datasheet.

    Regards,
    I.K.