Use DS160PT801*2pcs for PCIe Gen4 16 Lanes design

Sean Liao (Yu-Sheng)

Intellectual 1950 points

Other Parts Discussed in Thread: DS160PT801, CDCI6214, LMK00334

Hi,

My customer plan to use DS160PT801*2pcs for PCIe Gen4*16 Lanes design.

There are few questions as below:

1. Do they need to add additional CLK buffer for PCIe CLK?

2. Does TI have PCIe Gen4 by 16 Lanes reference design?

Thanks!

over 6 years ago

0 Lee Sledjeski over 6 years ago

TI__Mastermind 43795 points

Hi,
For additional information please contact directly at lee.sledjeski@ti.com

0 Sean Liao (Yu-Sheng) over 6 years ago in reply to Lee Sledjeski

TI__Intellectual 1950 points

Hi,

Could you please suggest if customer need to add additional CLK buffer for PCIe CLK?

If yes, could you please suggest the the buffer solution?

Thanks!

0 Lee Sledjeski over 6 years ago in reply to Sean Liao (Yu-Sheng)

TI__Mastermind 43795 points

Our current hardware solution uses a PCIe clock buffer to provide a PCIe clock to each retimer clock input.
Regards,
Lee

0 Lee Sledjeski over 6 years ago in reply to Sean Liao (Yu-Sheng)

TI__Mastermind 43795 points

We use a CDCI6214 clock generator and a LMK00334 clock buffer in our design.
Regards,
Lee

0 Sean Liao (Yu-Sheng) over 6 years ago in reply to Lee Sledjeski

TI__Intellectual 1950 points

hi Sledjeski,

Customer considers for using LMK00334 as clock buffer.

Could you please comment the limit of trace length of LMK00334?

Thanks a lot!

0 Lee Sledjeski over 6 years ago in reply to Sean Liao (Yu-Sheng)

TI__Mastermind 43795 points

Hi,

Since the CLK signals are only 100MHz the trace limit is not too strict. PCIe testing specifications use a transmission line characteristic of -15dB @ 4 GHz. For normal FR4 PCB material this is about 16" or 40cm.

Regards,

Lee

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Use DS160PT801*2pcs for PCIe Gen4 16 Lanes design