Hello TI
I am looking at 
section 6.9 Power-Up and Operation Timing Requirements.
In there it shows that Vdd/Vcc (1.2V) must be enabled first there after Vcc/Vdd (3.3V) which must be stable at most 200 us after.
Now take a look at TMDS181 Evaluation Module. In there there is a reference schematic. Figure 11 says VDD_1P1V and VCC_3P3V. Now take a look at Figure 16. VDD_1P1V is generated from BOARD_3P3V which is the same as VCC_3P3V.
This means that Vcc/Vdd (3.3V) is enabled first then Vdd/Vcc (1.1V) which is the opposite described in TMDS181 datasheet. The reference in evaluation module is contradicting the power timing sequence in TMDS181 datasheet.
Questions:
1. Which power timing sequence is the recommended? Can you please clarify.
2. Violating the timing sequence (as the evaluation module), what is the side effect.
Br
Imre
