TUSB4041I: VDD VDD33 and GRST Power up timing

Betty Guo

Part Number: TUSB4041I

Hi,

customer use TUSB4041I, has below quesitons, could you give some comments?

1. in the datasheet, below table 7.6, the (2) say the VDD must be stable minimum of 10us before VDD33, but the figure 1 show the VDD33 should be stable before VDD. I'm confuse about it. which one is normal power -up timing? Meanwhile, the page 14, 8.3.7 say, the device does not specific power sequencing requirements. I wonder if there any mistaks?

2. what's the meaning of tsu-io and thd_io?

3. customer place 1uF in GRST pin, VDD and VDD33 power up at the same time, one board can work and other one not. Why?

4.They use external circuit to control GRST voltage, GRST=0 before VDD and VDD33 stable, and then wait 3ms, pull GRST to high. in this condition, circuit can work properly. is there any potential risks?

thanks for your attention.

over 7 years ago

0 Brian Zhou over 7 years ago

TI__Guru**** 161746 points

Vdd33 should be stable before Vdd.
Tsu is setup time and Thold is hold time for datapin relative to clock signal.

0 JMMN over 7 years ago

TI__Guru 60870 points

The important requirement is that both power rails are stable for approximately 3ms before GRSTz goes high. If there is an actively driven GRSTz signal, then power sequencing does not matter. If GRSTz is being generated by a passive circuit consisting of an external capacitor and an internal pullup resistor, the issue with VDD33 ramping before VDD is that the internal pullup resistor is tied to the VDD33 rail and the GRSTz line may be pulled high before VDD finishes ramping. On the EVM design, VDD33 and VDD ramp almost simultaneously, so this is not a concern.

A3# If a 1 uF capacitor is not providing an adequate reset, check the GRSTz timing, it may need to be increased to 2.2 uF.
A4# Also, an active GRSTz will always work.

Regards,
JMMN

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TUSB4041I: VDD VDD33 and GRST Power up timing