• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 33 subscribers
  • Views 476 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83620: DP83620 Pin's status during power up

Sulyn ZHANG
Expert 8700 points
Part Number: DP83620


Hi Team,

My customer is planning to use DP83620 in new project. One quick question I want to confirm with you that during Power up(before the steady status), what's the output status for Pin RXD0, RXD1, CRS_DV and RX_ER? Will they be high impedance or low/high voltage?

Why asking this is because that DP83620 is connected to FPGA(To work as MAC), but due to power sequence, FPGA's power supply will be after DP83620's power supply, customer is worrying about that if these pins are high voltage, these maybe current flow through these pins to FPGA as FPGA's pin are not high impedance when unpowered. Thus may damage the FPGA.

Thanks a lot for your suggestions or solution to solve this consideration from customer!

Best regards,

Sulyn

  • 0
    TI__Expert 5670 points
    Hi Sulyn,

    For this application, I'd suggest to configure the DP83620 into MII Isolate mode. In this mode, output pins (RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and CRS/CRS_DV) will be high impedance when the device is powered up. See section 5.5.1 for more details about MII Isolate Mode.

    Regards,

    Hung Nguyen
  • 0 in reply to Hung Nguyen92
    TI__Expert 8700 points

    Hi Hung,

    Many thanks for the suggestion. This should be helpful. But I still a little bit confused that:

    1. It seems DP83620 need to be strapped to address 0 to use the MII isolated mode. But if customer don't want to use address 0 for DP83620, how to do with this?

    2. If customer already finished the schematic and can't strapped the DP83620 to address 0, any solution to resolve this situation?

    3. Since the MII isolated mode is just for protection, after normal power up, can customer write the 0 to bit 10 of the BMCR register to be out of MII isolate mode and back to normal mode?

    Thanks a lot for the support!

    Best regards,

    Sulyn

  • 0 in reply to Sulyn ZHANG
    TI__Expert 5670 points
    Hi Sulyn,

    1. You are correct that the MII isolate mode only works with PHY address 0.

    2. Since the PHYAD[0] pin has weak internal pull-up resistor and PHYAD[4:1] pins have weak internal pull-down resistors, the default setting for the PHY address is 1. To configure to PHY address 0, only one external pull-down resistor is needed on COL pin.

    3. Yes, after normal power up, writing 0 to bit 10 of BMCR register will cause the device going back to normal mode.

    Regards,

    Hung Nguyen
  • 0 in reply to Hung Nguyen92
    TI__Expert 8700 points

    Hi Huang,

    Many thanks for further input, its very clear to me now. But here comes another question:

    As customer will use 4pcs DP83620. You know customer can't configure all 4 DP83620 to address 0, so do you have some suggestions to resolve this problem and go ahead ....?

    Many thanks!

    Best regards,

    Sulyn

  • 0 in reply to Sulyn ZHANG
    TI__Expert 5670 points
    Hi Sulyn,

    If there are multiple DP83620 devices in the design, I would suggest using FPGA to control the RESET_N or PWRDOWN pin of DP83620 devices. Configure the system in the way that upon powering up, all DP83620's will be in reset or power down mode. After the FPGA is powered up, it can release the reset or power signals.

    Regards,

    Hung Nguyen