Other Parts Discussed in Thread: TLK10232
Our setup for the TLK10031 is:
- HS side: connected using SFP+ optical connector to the SFP+ of another PCI card connected to a PC at 10G rate.
- LS side: connected to 4 channels XAUI for TX and 4 channels for RX at rate of 3.125 Gbps implemented on a Zynq7000 FPGA. A 10GbE MAC IP is also implemented.
- MDIO signals: connected to the FPGA.
- Reference clock is connected to an 156.25 MHz oscillator.
- ST, Mode_SEL and PRBSEN are connected to pin headers and can be set as needed.
- TESTEN is pulled low.
What we were able to achieve:
1. Communicate with the PHY using MDIO to read registers and configure CLKOUT. We were able to receive CLKOUT successfully.
What we are trying to achieve:
1. Follow specific bring up procedures to get our test setup mentioned above to fully work. We found this 4048.tlk10232_BringupProcedures_v2.pdf document but we couldn't find the procedures suitable for our setup. Can you please point to which of the mentioned cases is suitable to us or guide us on how to get this setup to run successfully?
Your help is much appreciated.
Regards.