DS90UB947-Q1: Setup time and hold Time ?

Hi,

OpenLDI is also serdes I/f, not strict request on setup/hold timing. pls check d/s on the LVDS_CLK and LVDS_Data relationship as below.

8.3.4 OpenLDI Input Frame And Color Bit Mapping Select
The DS90UB947-Q1 can be configured to accept 24-bit color (8-bit RGB) with 2 different mapping schemes,
shown in Figure 13 and Figure 14. Each frame corresponds to a single pixel clock (PCLK) cycle. The LVDS clock
input to CLK± follows a 4:3 duty cycle scheme, with each 28-bit pixel frame starting with two LVDS bit clock
periods high, three low, and ending with two high. The mapping scheme is controlled by MAPSEL strap option or
by Register (Table 10).
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best regadrs,

Steven