DS90UA102-Q1: SCK = 1/2 SER Clock

Charley san

Thank you for your update.
OK, we will try it.

Kind regards,

Hirotaka Matsumoto

Charley san

Thank you for your cooperation.

The customer could confirm that they have some wrong power up seqence.
There is the description on the datasheet P33 that "The PDB pin must be held low until the power supplies (VDDn and VDDIO) have settled to the recommended operating voltage.".
On the customer's sequence, until the power supplies (VDDn and VDDIO) have settled to the recommended operating voltage, PDB pin was high for an instant.
After changing the power up sequence, the problem went away.

We would like to know follows as the reference;
Serializer(101-Q1) and Desrializer(102-Q1) should operate the same power up sequence.
"The PDB pin must be held low until the power supplies (VDDn and VDDIO) have settled to the recommended operating voltage."
Does this problem(1/2 SCK) arise from Des device or Ser device?
Of cource, the customer operates the correct power sequence, however they would like to know the detail cause of this problem.

Kind regards,

Hirotaka Matsumoto

Charley san

We guess that your days are so busy, however could you give us the reply for our last update?
And then, we will get the waveform which is the startup with problem occurred.

Kind regards,

Hirotaka Matsumoto

Charley san

Thank you so much for your reply.
We have some wrong information.

Could you refer to the attachment file?
20190115_DS90UA101-Q1.pdf

Kind regards,

Hirotaka Matsumoto

Matsumoto-san,

I would like to request a few more items.

1. A zoomed in power sequencing waveform for both Ser and Des showing VDD11, VDDIO, and PDB. 

2. Is any of GPO[3:0] drived high or low before power up?

3. Any pull-up/pull-down resistors on GPO[3:0]

Best Regards,

Charley Cai

Charley san

Thank you for your reply!


1. A zoomed in power sequencing waveform for both Ser and Des showing VDD11, VDDIO, and PDB. 
->Could you refer to the attachement file P2?
   SER and Des are the same power sequence. 
20190116_DS90UA101-Q1.pdf

2. Is any of GPO[3:0] drived high or low before power up?
3. Any pull-up/pull-down resistors on GPO[3:0]
    ->Just in case, we would like to confirm one point.
       Do you need the information GPO[3:0] drived high or low before power up only? Do you need GPIO[3:0] information also?

Kind regards,

Hirotaka Matsumoto

Charley san

Thank you for your reply.

Please refer to the attachment file P4.

8244.20190116_DS90UA101-Q1.pdf

Kind regards,

Hirotaka Matsumoto

Charley san

Thank you for your DS90UA102-Q1 and DS90UA101-Q1's support always!

Could you give us your circumstance?
We would like to send you the wave form which shows SCK and Dout with PDB and without PDB operation using private message on E2E.
It might contatin customer's confidential contents, sou could you accept our frirend request?

Kind regards,

Hirotaka Matsumoto