Team,
My customer is questioning the internal PLL jitter performance, which is not listed in the spec.
If they supply REFCLK in with 19.2MHz clock, and the clock phase noise is
-90dBc@10Hz, -100dBc@100Hz, -110dBc@1kHz,-125dBc@1MHz,-135dBc@5MHz. And they are asking about the 60MHz output clock's jitter. Could we provide?
Best Regards,
Peter Wei
