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DP83867IR: Discrete Magnetics Layout.

John Lally
Intellectual 600 points
Part Number: DP83867IR

Our application is highly customized with extreme size constraints and requires discrete magnetics, so we’re forced to place the DP83867IRRGZT on the backside of our pcb directly opposite the magnetics (Pulse Eng Part No: HX5120NL).   Our PCB has 20 layers so we’re thinking of routing chassis ground under the magnetics on layer 2, and routing circuit ground under the DP83867IRRGZT on layer 19. The intent is to use chassis ground and circuit ground to shield the DP83867IRRGZT/traces from the magnetics, while still getting ~50mils of separation (distance from layer 2 to 19) between chassis ground and circuit ground. Can you please let us know if this is viable, or if not what the issues with this approach are?   BTW, we did see the note in Fig. 40, pg 118 of the datasheet calling for power/ground planes to be voided under the transformer but we’re very concerned that if the planes are voided, in our case fields from the transformer will couple into the DP83867/traces opposite the transformer because the transformer and DP83867 are directly opposite each other on top and bottom of the pcb.

Thanks -John

  • 0
    TI__Mastermind 23675 points
    Hi John,

    We have not built a board like what you described above.
    The relative permeability of copper is ~1 (same as air). You won't get any additional shielding from the copper plane because its a conductor.
    I am not sure how deep the magnetic field will penetrate into your board since this is material dependent.
    What I do recommend is for you to see if there are any available magnetics you can procure with a bottom shield to help suppress the field.
    Unfortunately I can not say for certain if it will or will not cause issue.
  • 0 in reply to Ross Pimentel
    Intellectual 600 points

    Hi Ross,
    Is it possible to use the DP83867IR "Magneticless" i.e. ac coupled with capacitors?

    If yes, are there any constraints: Max Length?, fixed data rate?, no auto-negotiate? etc...

    Our length is less than 1 Meter, & we could fix our rate at 100Mbps if need be.

    We're working with a processor that lists only 10/100/1000 Ethernet Phy's as supported and there's a lot of legacy with the DP83867 with our processor, so we're reluctant to design it out.

    Thanks again,
    -John

  • 0 in reply to John Lally
    TI__Mastermind 23675 points
    Hi John,

    The DP83867IR can operate with transformerless in 10BASE-T and 100BASE-TX modes.
    It is not able to operate with transformerless in 1000BASE-T mode.

    This device can meet your 1m cable 100Mbps fixed speed need.
  • 0 in reply to Ross Pimentel
    Intellectual 600 points

    Thanks Ross,

    Just a few more questions if i may:

    1.)    For our fixed 100Base-TX transformerless implementation we plan on using the DP83867IR TD_P/M_A and TD_P/M_B pins, leaving TD_P/M_C and TD_P/M_D open. Is this correct?

    2.)    Given our transformerless implementation are any external biasing and/or terminations required between the ac capacitors and the DP83867IR or are they internal to the DP83867IR?

    3.)    In our application both ends of the link will share a common ground reference, we plan on using a 100nF AVX ESD51C104K4T2A-24 as the ac coupling cap. This part is rated for 100V, with a 24kV ESD rating in a 0805 package.   It’s our understanding that since we have a common ground reference the Ethernet isolation voltage requirements don’t necessarily apply but ESD issues do apply due to cable mates/unmates. Given a transformerless design, do you believe we have achieved a robust implementation?

    Thanks,

    -John

  • 0 in reply to John Lally
    TI__Mastermind 23675 points
    Hi John,

    A1) Yes, that it correct.

    A2) No external bias or termination needed.

    A3) If you have a shared ground, you might see ground loop issues if the cable you are using is shielded (CAT6). What level of ESD do you expect to see in your system and what level of protection have you added to your design?