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TUSB564: Question about TUSB564 configuration

Gabriel Xu
Intellectual 2145 points
Part Number: TUSB564
Other Parts Discussed in Thread: TUSB1064

Hi teams

My customer is using TUSB564 for new design as DP sink device re-driver.

They use a MacbookPro as DP source and connect with DP sink device with a 1.5 meter long cable.

They found the display picture unstable in the DP sink device.

Below is the question:

  1. Lowest input DP differential voltage level(peak to peak) in TUSB564 input side to ensure robust DP signal transfer?
  2. Do you have any guideline about how to tuning the EQ parameter to achieve the best robustness?
  3. In datasheet application circuit(Figure.27) there is no AC-coupling capacitor between RX1/RX2 pairs, i wondering why?
  4. There is no impedance matching guidance for DP and USB port, but I found the guidance for TUSB1064. In this document it indicates that the length between Type-c connector and TUSB1064 should less than 2 inch with 90 ohm differential resistance. And USB port to device should less than 6 inch and DP to device should less than 8 inch. Are the requirement is the same to TUSB564?
  5. The timing requirement spec for the signal after re-driver? (How to confirm the signal after our re-driver is meet DP1.4 standard if we don't have the mask for the eye diagram?

Thanks in advance.

  • 0
    TI__Guru**** 178996 points

    Gabriel

    What is the DP data rate, 5.4G or 8.1G?

    If the customer reduces the cable length to less than 1.5m, does it resolve the video instability issue?

    There are several EQ associated with TUSB1064, please make sure they are tuning the DPEQ parameter

    1. Please refer to DP and DP_CTS spec, TP3/TP3_EQ is being defined at the connector and is normative. TP4 is being defined at the RX pin, but is informative. so for TP3/TP3_EQ
    Voltage Level =
    90mV pk-pk +/-10% (HBR2 at TP3_EQ)
    150mV pk-pk +/-10% (HBR at TP3_EQ)
    46mV pk-pk +/-10% (RBR at TP3)

    2. There are several ways to validate the robustness of a DP sink design while tune the DPEQ parameter
    a. Run DP RX Jitter Tolerance test (JTOL), look at the bit error rate for different DPEQ paramter
    b. Look at the link training, look at the link training result for different DPEQ parameter
    c. Look at the sink video output, make sure video is stable for different DPEQ paramter

    3. This assumes AC-coupling capacitors are populated on the corresponding TX pairs.

    4. The DP 8in given in the TUSB1064 configuration guide is an example on how to estimate the initial setting of TUSB1064 DPEQ equalizer, it does not mean the max DP trace length is 8in. Max length is determined by source TX and sink RX capability, PCB loss, connector loss, etc. You can use the same method to estimate the initial setting of TUSB564 DPEQ equalizer. What is the loss of the 1.5m cable?

    5. Please see answer to question#2, since this is a sink application, instead using eye diagram to validate the signal integrity, RX Jitter Tolerance Test will be used.

    Thanks
    David

  • 0 in reply to David (ASIC) Liu
    TI__Intellectual 2145 points
    Hi David
    Thanks for your replys.
    What "TP3_EQ" means? What customer want to know is do we have any reqirement for TX/RS pin input differential voltage level?
    Do you have further guidance documents about how to check the bit error rate in JTOL test?
    So do you mean that the maximum length between sink side type-C connector and TUSB564 could larger than 8inchs if the source is strong enough?
    Do you have technical docusments about jitter tolenrance test could share to me?
    Thanks.
  • 0 in reply to Gabriel Xu
    TI__Guru**** 178996 points
    Gabriel

    TP3_EQ means after equalizer. At 2.7G and 5.4G data rate, the eye may be closed after a cable that has a large loss within the DP spec. So a equalizer function is applied to the close eye to open it up.

    So the input differential voltage level will be
    90mV pk-pk +/-10% (HBR2 at TP3_EQ)
    150mV pk-pk +/-10% (HBR at TP3_EQ)
    46mV pk-pk +/-10% (RBR at TP3)

    Do you have a DP CTS spec? This is probably the best place to look for the info on JTOL test. You can also take a look at this doc for high level discussion of DP RX JTOL test: literature.cdn.keysight.com/.../5990-5487EN.pdf.

    The 8in is between TUSB1064 and DP RX, but the info being presented in TUSB1064 app note is not correct and needs to be updated. In the case of TUSB564 which supports both USB and DP, even though the distance between Type C connector and TUSB564 can be longer from DP perspective (loss can be handled by the DP equalizer with max at 12.1dB@4.05GHz), the distance may be limited by the USB usage.

    Thanks
    David