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DS90UB913A-Q1: PCLK limitation for DS90UB913A-Q1

Part Number: DS90UB913A-Q1

Hi,

I have connected imager to DS90UB913A-Q1. Its working at 1280*720@60FPS with 10 bit RAW mode with DVP inputs. PCLK for it comes to around 74.25MHz based on standard timing calculations. But DS90UB913A-Q1 data sheet suggests I need to have pixel clock twice "GPIO3 XCLKIN". For my case "GPIO3 XCLKIN" frequency is 48MHz which requires PCLK to be 96MHz which may not be exactly possible by adding all the active and blanking pixels. Please let me know if this is a hard requirement. 

Regards,

Hardik Shah 
 

  • Hello Hardik,

    In applications where the DS90UB913A-Q1 device is operated from an external oscillator, the divide-by-2 clock output feeds the imager device through GPO2 pin.
    The pixel clock to external oscillator ratios needs to be fixed for the 12–bit high frequency mode and the 10–bit mode. In the 10-bit mode, the pixel clock frequency divided by the external oscillator frequency must be 2.
    In the 12-bit high frequency mode, the pixel clock frequency divided by the external oscillator frequency must be 1.5. For example, if the external oscillator frequency is
    48 MHz in the 10–bit mode, the pixel clock frequency of the imager needs to be twice of the external oscillator frequency, that is, 96 MHz. If the external oscillator frequency is 48MHz in the 12-bit high frequency mode, the pixel clock frequency of the imager needs to be 1.5 times of the external oscillator frequency, that is, 72 MHz