TLK2711-SP: Data swap problem

Changhun,
The likely causes are wrong mapping of signals, either on the board or in FPGA that is decoding the data.
It is key that the K28.5 is transmitted on the LSB, as it has the comma character and is responsible for aligning the serial data to the parallel word boundary. If it is sent on the MSB, it would cause the the MSB to be mapped to the LSB on the receiver.
Please see this application note with a few more details. It is located in the TLK2711-SP product folder.
www.ti.com/.../technicaldocuments
Direct link: www.ti.com/.../sgla001

If this answers your question, please click "Verify it as the answer"
Regards,
Wade

We set of TKMSB 'LOW' and TKLSB 'HIGH'.
And then 16bit data (C5BC) sending D5.6(MSB) and K28.5(LSB).
But receiver get swap data of BCC5.

Changhun,

This should not be possible.

Have you verified that correct logical and physical mapping exists from transmitter parallel pins to TLK2711?

Also verify receiver physical and logical mapping to FPGA.

Can you describe the hardware you are using to test?  Schematic?

Regards,

Wade

Logical and physical mapping have not problem.

This is my schematic.

Please check and advise me.

Changhun,
I see that you are transmitting from TLK2711 to the FPGA and decoding within the FPGA.
If the comma is being sent on the LSB, then the job of the FPGA will be to see this comma, and create proper byte alignment within the FPGA.

This issue is related to the IP in the FPGA, and not the transmission from the TLK2711.

Regards,
Wade

I also notice that you are driving the TLK2711 GTX_CLK with an clock from the FPGA. This likely does not meet the input jitter requirements of the TLK2711. The datasheet indicates that max pk-pk jitter of 40ps as input condition for clock. This likely will work, but will result in a link with a higher BER.
Regards,
Wade

There are a couple options to help show you where the issue lies.

1) You can duplicate transmission using twoTLK2711EVM-CVAL boards transmitting same data.  It will make it clear that your FPGA is not decoding comma into byte alignment properly.   You can do this with one evm as well in external (or internal) loopback.

2) You can also try (if possible) to enable internal loopback and examine the RX data.  It should show that the TLK2711 is decoding the MSB and LSB properly.  You will need to bring LCKREFN high to enable the receiver along with LOOPEN (for internal loopback).  If you can do this, the RXD pins will drive the data received on the link and you can examine with scope.   THis looks like you can do with by modifying the pullup/down resistor biasing for these inputs.

Another thing I noticed, is that you will not be able to properly perform the power up reset with your current schematic.  It is necessary to activate the receiver (via loopen, or real RX data) to insure that the receiver is reset after power up.  See section 8.3.20 in the datasheet for more information.

Regards,

Wade