TPIC8101: The INT / HOLD terminal

Kenji Ohno1

Genius 5095 points

Part Number: TPIC8101

Hi Team,

The INT / HOLD terminal is set to output or hold from the integration stage.

Where is the extraction done in the block diagram?

Is it "Programmable Integrator"?

Best Regards,

Kenji

over 5 years ago

0 Bala Ravi over 5 years ago

TI__Expert 6625 points

Hi Kenji,
We've got your request. One of our device experts will get back to you soon.

Best Regards,
Bala Ravi

0 Kenji Ohno1 over 5 years ago in reply to Bala Ravi

Genius 5095 points

Hi,

Your immediate response is highly appreciated.

Best Regards,
Kenji

0 Clancy Soehren over 5 years ago

TI__Mastermind 23810 points

The output of the "programmable integrator" is the output of the TPIC8101. When INT/HOLD is high, it is in integrate mode, so the integrator will accumulate. When INT/HOLD is low, it is in hold mode, and the output will remain constant (to allow the MCU time to sample the data). When INT/HOLD is raised high again, the integrator will be cleared and it will start from zero.

Hopefully this makes it a little more clear!

0 Kenji Ohno1 over 5 years ago in reply to Clancy Soehren

Genius 5095 points

Hi Clancy,

Thank you for your reply.

However, what I wanted to know is the delay time that is supposed to occur when changing the integration mode when INT / HOLD is changed from low to high.

Since there is a filter up to "Programmable Integrator", I think that delays will occur as shown in the figure.

There was no information on the regulation in this datasheet.

Delay time.pdf

Best Regards,

Kenji

0 Clancy Soehren over 5 years ago in reply to Kenji Ohno1

TI__Mastermind 23810 points

There are two relevant specs. The first is the sampling frequency of the ADC and DAC, which is nominally 200kHz. The second relevant spec is the settling time for the output buffer (if you are using the analog output). Between the ADC and DAC is a DSP.

I do not know the delay for the INT/HOLD sampling, but it should be at least an order of magnitude faster than those other two parameters.

The INT/HOLD frequency is usually slow enough that these delays should not matter. Just make sure to wait a reasonable amount of time after INT/HOLD goes low before sampling the data.

0 Kenji Ohno1 over 5 years ago in reply to Clancy Soehren

Genius 5095 points

Hi Clancy,

Thank you for your answer.

My customer have begun consideration for using the device.

I understood that there really is a delay time.

If possible, can you measure delay time of this device?

I would like to see concrete performance data.

Best Regards,

Kenji

0 Clancy Soehren over 5 years ago in reply to Kenji Ohno1

TI__Mastermind 23810 points

Kenji,

What is the purpose of this request? Is waiting at least the settling time (20us) too long? Note that when INT/HOLD is held low, the output data is held constant, so the delay does not matter (besides that they wait at least 20us before sampling).

0 Kenji Ohno1 over 5 years ago in reply to Clancy Soehren

Genius 5095 points

Hi Clancy,

It is preferable that the input is not delayed in order to decide the INT / HOLD signal from the rotation of the engine.

Regards,
Kenji

0 Clancy Soehren over 5 years ago in reply to Kenji Ohno1

TI__Mastermind 23810 points

Kenji,

Unfortunately, I cannot supply more information than what is in the datasheet. The settling time is the closest spec to what you are asking for, which is a maximum of 20us.

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TPIC8101: The INT / HOLD terminal