• State Resolved
  • Locked Locked
  • Replies 22 replies
  • Answers 3 answers
  • Subscribers 34 subscribers
  • Views 2239 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83867IR: Trying to get DP83867 to auto negotiate.

Corey Hahn60
Prodigy 220 points
Part Number: DP83867IR

Phy is connected to a ZynqMP chip.  In uboot, mii dump produces:

ZynqMP> mii info c
PHY 0x0C: OUI = 0x80028, Model = 0x23, Rev = 0x01, 10baseT, HDX
ZynqMP> mii dump c 0
0. (1140) -- PHY control register --
(8000:0000) 0.15 = 0 reset
(4000:0000) 0.14 = 0 loopback
(2040:0040) 0. 6,13 = b10 speed selection = 1000 Mbps
(1000:1000) 0.12 = 1 A/N enable
(0800:0000) 0.11 = 0 power-down
(0400:0000) 0.10 = 0 isolate
(0200:0000) 0. 9 = 0 restart A/N
(0100:0100) 0. 8 = 1 duplex = full
(0080:0000) 0. 7 = 0 collision test enable
(003f:0000) 0. 5- 0 = 0 (reserved)


ZynqMP> mii dump c 1
1. (7949) -- PHY status register --
(8000:0000) 1.15 = 0 100BASE-T4 able
(4000:4000) 1.14 = 1 100BASE-X full duplex able
(2000:2000) 1.13 = 1 100BASE-X half duplex able
(1000:1000) 1.12 = 1 10 Mbps full duplex able
(0800:0800) 1.11 = 1 10 Mbps half duplex able
(0400:0000) 1.10 = 0 100BASE-T2 full duplex able
(0200:0000) 1. 9 = 0 100BASE-T2 half duplex able
(0100:0100) 1. 8 = 1 extended status
(0080:0000) 1. 7 = 0 (reserved)
(0040:0040) 1. 6 = 1 MF preamble suppression
(0020:0000) 1. 5 = 0 A/N complete
(0010:0000) 1. 4 = 0 remote fault
(0008:0008) 1. 3 = 1 A/N able
(0004:0000) 1. 2 = 0 link status
(0002:0000) 1. 1 = 0 jabber detect
(0001:0001) 1. 0 = 1 extended capabilities


ZynqMP> mii dump c 2
2. (2000) -- PHY ID 1 register --
(ffff:2000) 2.15- 0 = 8192 OUI portion


ZynqMP> mii dump c 3
3. (a231) -- PHY ID 2 register --
(fc00:a000) 3.15-10 = 40 OUI portion
(03f0:0230) 3. 9- 4 = 35 manufacturer part number
(000f:0001) 3. 3- 0 = 1 manufacturer rev. number


ZynqMP> mii dump c 4
4. (01e1) -- Autonegotiation advertisement register --
(8000:0000) 4.15 = 0 next page able
(4000:0000) 4.14 = 0 (reserved)
(2000:0000) 4.13 = 0 remote fault
(1000:0000) 4.12 = 0 (reserved)
(0800:0000) 4.11 = 0 asymmetric pause
(0400:0000) 4.10 = 0 pause enable
(0200:0000) 4. 9 = 0 100BASE-T4 able
(0100:0100) 4. 8 = 1 100BASE-TX full duplex able
(0080:0080) 4. 7 = 1 100BASE-TX able
(0040:0040) 4. 6 = 1 10BASE-T full duplex able
(0020:0020) 4. 5 = 1 10BASE-T able
(001f:0001) 4. 4- 0 = 1 selector = IEEE 802.3


ZynqMP> mii dump c 5
5. (0000) -- Autonegotiation partner abilities register --
(8000:0000) 5.15 = 0 next page able
(4000:0000) 5.14 = 0 acknowledge
(2000:0000) 5.13 = 0 remote fault
(1000:0000) 5.12 = 0 (reserved)
(0800:0000) 5.11 = 0 asymmetric pause able
(0400:0000) 5.10 = 0 pause able
(0200:0000) 5. 9 = 0 100BASE-T4 able
(0100:0000) 5. 8 = 0 100BASE-X full duplex able
(0080:0000) 5. 7 = 0 100BASE-TX able
(0040:0000) 5. 6 = 0 10BASE-T full duplex able
(0020:0000) 5. 5 = 0 10BASE-T able
(001f:0000) 5. 4- 0 = 0 selector = ???

Cannot get the chip to auto negotiate at all.  Several cables, routers, and laptops tested.

Tried to force A/N with mii write  c 0 0x1340 with no luck.  

Is there something i can probe or check to debug this?

  • 0
    TI__Expert 5670 points
    Hi Corey,

    When you say the chip cannot auto negotiate, I'm assuming you encountered no link issue. The common mistake is that Auto-Negotiation is disabled by strap option.

    In order to confirm it, can you read register 0x6E and 0x6F?

    Regards,

    Hung Nguyen
  • 0 in reply to Hung Nguyen92
    Prodigy 220 points
    I cannot link or connect in any way. 10T half duplex up to 1G full duplex.
    There is no register 0x6E and 0x6F?

    ZynqMP> mii read c 0xe
    0008
    ZynqMP> mii read c 0xf
    3000
    ZynqMP> mii read c 0x6
    0064
  • 0 in reply to Corey Hahn60
    TI__Expert 5670 points

    Hi Corey,

    Register 0x6E and 0x6F are defined in the datasheet.

    Can you tell me how you strap RX_DV/RX_CTRL pin on your board?

    Regards,

    Hung Nguyen

  • 0 in reply to Hung Nguyen92
    Prodigy 220 points

    ZynqMP> mii read c 0x6e
    FFFF
    ZynqMP> mii read c 0x6f
    FFFF
    ZynqMP> mii read c 0
    1140

    I did attempt to read the registers but it came back all 1's.

    RX_DV/RX_CTRL is pulled down to ground with a 1k ohm resistor and nothing installed to pull it up to the I/O rail.

    ----edit

    tried to read in decimal..

    ZynqMP> mii read c 110
    4040
    ZynqMP> mii read c 111
    0302

    --- edit again

    So this doesn't match up.  According to the schematics provided by the maker, every strap is floating except, 

    RX_DV/RX_CTR, pulled down only

    RX_D0, pulled down with 1k only

    RX_D2, pulled up with 1k only

    -- yet again

    ZynqMP> mii read 0xc 0x006e
    FFFF
    ZynqMP> mii read 0xc 0x006f
    FFFF

    reading with the address in hex seems to be the correct option.  but the All 1's returned is not making sense to me.

    Something is wrong with my reading of these registers.

    ZynqMP> mii read 0xc 0x25
    FFFF
    ZynqMP> mii read 0xc 0x0025
    FFFF

    Above about 0x1F.  It seems hosed.

    -- more data

    ZynqMP> mii read 0xc 0x00-0x70
    addr=0c reg=00 data=1140
    addr=0c reg=01 data=7949
    addr=0c reg=02 data=2000
    addr=0c reg=03 data=A231
    addr=0c reg=04 data=01E1
    addr=0c reg=05 data=0000
    addr=0c reg=06 data=0064
    addr=0c reg=07 data=2001
    addr=0c reg=08 data=0000
    addr=0c reg=09 data=0300
    addr=0c reg=0a data=0000
    addr=0c reg=0b data=0000
    addr=0c reg=0c data=0000
    addr=0c reg=0d data=401F
    addr=0c reg=0e data=0008
    addr=0c reg=0f data=3000
    addr=0c reg=10 data=4040
    addr=0c reg=11 data=0302
    addr=0c reg=12 data=0000
    addr=0c reg=13 data=0040
    addr=0c reg=14 data=29C7
    addr=0c reg=15 data=0000
    addr=0c reg=16 data=0000
    addr=0c reg=17 data=0040
    addr=0c reg=18 data=6150
    addr=0c reg=19 data=4444
    addr=0c reg=1a data=0002
    addr=0c reg=1b data=0000
    addr=0c reg=1c data=0000
    addr=0c reg=1d data=0000
    addr=0c reg=1e data=0002
    addr=0c reg=1f data=0000
    addr=0c reg=20 data=FFFF
    addr=0c reg=21 data=FFFF
    addr=0c reg=22 data=FFFF
    addr=0c reg=23 data=FFFF
    addr=0c reg=24 data=FFFF
    addr=0c reg=25 data=FFFF
    addr=0c reg=26 data=FFFF
    addr=0c reg=27 data=FFFF
    addr=0c reg=28 data=FFFF
    addr=0c reg=29 data=FFFF
    addr=0c reg=2a data=FFFF
    addr=0c reg=2b data=FFFF
    addr=0c reg=2c data=FFFF
    addr=0c reg=2d data=FFFF
    addr=0c reg=2e data=FFFF
    addr=0c reg=2f data=FFFF
    addr=0c reg=30 data=FFFF
    addr=0c reg=31 data=FFFF
    addr=0c reg=32 data=FFFF
    addr=0c reg=33 data=FFFF
    addr=0c reg=34 data=FFFF
    addr=0c reg=35 data=FFFF
    addr=0c reg=36 data=FFFF
    addr=0c reg=37 data=FFFF
    addr=0c reg=38 data=FFFF
    addr=0c reg=39 data=FFFF
    addr=0c reg=3a data=FFFF
    addr=0c reg=3b data=FFFF
    addr=0c reg=3c data=FFFF
    addr=0c reg=3d data=FFFF
    addr=0c reg=3e data=FFFF
    addr=0c reg=3f data=FFFF
    addr=0c reg=40 data=FFFF
    addr=0c reg=41 data=FFFF
    addr=0c reg=42 data=FFFF
    addr=0c reg=43 data=FFFF
    addr=0c reg=44 data=FFFF
    addr=0c reg=45 data=FFFF
    addr=0c reg=46 data=FFFF
    addr=0c reg=47 data=FFFF
    addr=0c reg=48 data=FFFF
    addr=0c reg=49 data=FFFF
    addr=0c reg=4a data=FFFF
    addr=0c reg=4b data=FFFF
    addr=0c reg=4c data=FFFF
    addr=0c reg=4d data=FFFF
    addr=0c reg=4e data=FFFF
    addr=0c reg=4f data=FFFF
    addr=0c reg=50 data=FFFF
    addr=0c reg=51 data=FFFF
    addr=0c reg=52 data=FFFF
    addr=0c reg=53 data=FFFF
    addr=0c reg=54 data=FFFF
    addr=0c reg=55 data=FFFF
    addr=0c reg=56 data=FFFF
    addr=0c reg=57 data=FFFF
    addr=0c reg=58 data=FFFF
    addr=0c reg=59 data=FFFF
    addr=0c reg=5a data=FFFF
    addr=0c reg=5b data=FFFF
    addr=0c reg=5c data=FFFF
    addr=0c reg=5d data=FFFF
    addr=0c reg=5e data=FFFF
    addr=0c reg=5f data=FFFF
    addr=0c reg=60 data=FFFF
    addr=0c reg=61 data=FFFF
    addr=0c reg=62 data=FFFF
    addr=0c reg=63 data=FFFF
    addr=0c reg=64 data=FFFF
    addr=0c reg=65 data=FFFF
    addr=0c reg=66 data=FFFF
    addr=0c reg=67 data=FFFF
    addr=0c reg=68 data=FFFF
    addr=0c reg=69 data=FFFF
    addr=0c reg=6a data=FFFF
    addr=0c reg=6b data=FFFF
    addr=0c reg=6c data=FFFF
    addr=0c reg=6d data=FFFF
    addr=0c reg=6e data=FFFF
    addr=0c reg=6f data=FFFF
    addr=0c reg=70 data=FFFF

  • 0 in reply to Corey Hahn60
    TI__Expert 5670 points

    Hi Corey,

    If RX_DV/RX_CTRL pin is pulled down, the device is strapped to Not Applicable mode. We will not be able to guarantee PHY performance for Not Applicable mode.

    To enable Auto-Negotiation, RX_DV/RX_CTRL must be strapped to Mode 3.

    Regards,

    Hung Nguyen

  • 0 in reply to Hung Nguyen92
    Prodigy 220 points

    Changed resistor values to suggested for Mode 3. same behavior.  ie no change in behavior.

  • 0 in reply to Corey Hahn60
    TI__Expert 5670 points
    Hi Corey,

    You need to read back register 0x6E and 0x6F to confirm the straps are indeed correct. Refer to datasheet section 8.4.2.1 for how to read extended registers.

    Regards,

    Hung Nguyen
  • 0 in reply to Hung Nguyen92
    Prodigy 220 points
    ZynqMP> mii write c d 0x1F
    ZynqMP> mii write c e 0x6E
    ZynqMP> mii write c d 0x401f
    ZynqMP> mii read c e
    000C
    ZynqMP> mii write c d 0x1F
    ZynqMP> mii write c e 0x6F
    ZynqMP> mii write c d 0x401f
    ZynqMP> mii read c e
    0100

    Strap is correct.
    The bit set at the 8th bit wrong?
  • 0 in reply to Corey Hahn60
    TI__Expert 5670 points

    Corey,

    Can you provide the schematics showing DP83867 connectivity?

    Regards,

    Hung Nguyen

  • 0 in reply to Corey Hahn60
    TI__Expert 5670 points
    Hi Corey,

    Please refer to datasheet section 9.2.1.1 for Line Driver connection.

    The magnetic center tap should not be connected to any supply. Also, each center tap should have 0.1uF cap to GND. Please check the integrated MagJack you are using and make sure the integrated caps have recommended value.

    Regards,

    Hung Nguyen
  • 0 in reply to Hung Nguyen92
    Prodigy 220 points

    Fixed.  Still the same no auto-negotiate..

  • 0 in reply to Corey Hahn60
    TI__Expert 5670 points
    Hi Corey,

    How did you separate the center taps of the integrated magnetic? See figure 30 in the datasheet section 9.2.1.1. Each center tap of the magnetics should be independently de-coupled to ground via a 0.1uF capacitor.

    Can you also read register 0x31 if you have a chance?

    Regards,

    Hung Nguyen
  • 0 in reply to Hung Nguyen92
    Prodigy 220 points

    Not yet.  Trying to figure out how to cut them with the package given.

    ZynqMP> mii write c d 0x1f
    ZynqMP> mii write c e 0x31
    ZynqMP> mii write c d 0x401f
    ZynqMP> mii read c e
    0030

  • 0 in reply to Corey Hahn60
    Prodigy 220 points
    So after a power cycle the phy began working?!? Strange that I did nothing special before this power cycle. I will tag the strap fix and the disconnect of the center tap on the magnetic as the fix, but I am not quite sure i found the root cause.

    Thank you for your help Hung Nguyen.
  • 0 in reply to Corey Hahn60
    Prodigy 220 points

    Seems this problem is still not over.  The LEDs for link and gigabit are working and blinking but alas I cannot get any traffic to get through the phy.

    No responses from ping, no dhcp, no setting static addresses and working.  the router cannot see the zynq board.  The router also shows a good connection and a link at 1Gbit, but no traffic.

  • 0 in reply to Corey Hahn60
    TI__Expert 5670 points
    Hi Corey,

    Good to hear that you can get the 1G link!

    The 2nd issue you're seeing seems to be related to the MAC interface. Your board is designed for RGMII mode which has different settings for delay on both TX and RX direction. Depending on whether the RGMII MAC has any internal delay, delay setting on the PHY side needs to be configured accordingly. Please refer to Table 8 and Table 9 in datasheet for more details on RGMII Clock Skew configuration.

    From strap register readout you provided earlier, 0x6F = 0x100 which means both TX and RX having 2ns clock skew. In this case, the RGMII MAC must have 0 clock skew for the RGMII interface to work properly.

    You can also use registers to control the clock skew. Refer to this RGMII app note www.ti.com/.../snla243.pdf

    Regards,

    Hung Nguyen
  • 0 in reply to Hung Nguyen92
    Prodigy 220 points
    Exactly my problem. 0 clock skew is not realistic. I pushed it out to 2ns for both, and now i am in business. How should I set these skews if i do not have access to the routing and pcb information? Trial and error?
  • 0 in reply to Corey Hahn60
    TI__Expert 5670 points
    Hi Corey,

    I would suggest following this app note www.ti.com/.../snla243.pdf for more details regarding to RGMII timing on your system.

    Regards,

    Hung Nguyen
  • 0 in reply to Hung Nguyen92
    TI__Expert 5670 points
    Hi Corey,

    I haven’t heard back from you, I’m assuming you were able to resolve your issue. I will go ahead and close this thread.

    If you need further support, kindly open a new thread.

    Regards,

    Hung Nguyen
  • 0 in reply to Corey Hahn60
    Prodigy 60 points

    Hi I facing similar situation.

    I noticed that when your strap mode was 1. register 0x9 = 0x300, so I think you just need to add work around using register 0x0031 bit 7, as described in data sheet page 48  "RX_CTRL is not strapped to mode 3 or 4 in HW"

    This also patched in Linux kernel under ti,rxctrl_strap_quirk

    In my case and also matches the advised change setting to strap 3 or strap 4 ,  I'm getting reg 0x9 0x1300,( don;t now what you getting) when setting it manually to 0x300, master slave negotiation starts and link comes up. - but this is not described in TI datasheet so no guarantee... but seems to work in my case

    I'm  following this case cause I wonder what is the correct way.

    BTW my strap registers are 0x6e = 0x0085   and 0x6f 0x0100

    Regards

    Baruch

     

  • 0 in reply to baruch lerer
    Prodigy 60 points
    After some more investigation,

    Using RX_DV/RX_CTRL bootstarp mode 3 (and not 4) vitrified by 0x6e new val 0x05,

    I recommend to verify the bootstrap mode with register 0x6e, since the resistors set can have some inaccuracy,

    You can try to tune register with voltmeter readings hold the PHY in reset mode, according to bootstarp mode table.

    Master slave is also set to negotiation enable, verified by register 0x9 new val 0x300

    Now link is up, without any bit banging .

    Most driver automatically and independently set speed duplex auto negotiation, this fact mask the issue boostarp 4 is not recommended!!!

    The affect of bootstrap mode 3-4 on master/slave negotiation is unclear from pdf. seems that boot strap 3 enable master/slave negotiation as well.

    Regards

    Baruch