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DS90UB947-Q1: Questions about applying to 5-wire solutions

Part Number: DS90UB947-Q1

Hi team

My customers wants to apply DS90UB947 + DS90UB948 for the TFT LCD solution.
DS90UB947 is LVDS_D[0:7] and LVDS_CLK as input spec.

LVDS spec supported to AP that they used is as below.
- Resolution: 1920*1080p
- Pixel Clock: 40~160MHz
- LVDS_D[0:4] : 5Lane Data
- LVDS_CLK : 1Lane Clock

Input lane is not same.
Is it ok to design DS90UB947 + DS90UB948?
If not, please suggest me another solution.

Thank you.

  • On DS90UB947, you could put the device into Dual OLDI mode and only use 5 data lanes.

    For example, you could use 947 D[0:4], and the data will come out from 948 D[0:4].

    The constrain is VSYNC, HSYNC and DE signals have to go on data lane 2.

    Please look at 947 datasheet OpenLDI color bit mapping.


    Best Regards,
    Charley Cai