SN65DPHY440SS: Missing sync packets and changing LP-HS transition time

Jon Key

Hello,

My customer is evaluating the DPHY440 and is seeing a good output on the MIPI lanes at high speed, but is not seeing sync packets coming from lanes 1-3. Is there a difference between lane 0 and the other lanes?

Does the retimer look for these packets and ignore them on certain lanes?

Also their camera transitions from LP to HS faster than the DPHY440 (40ns vs 60ns) are there settings on the DPHY440 to adjust this?

Thank you,

Jon

over 7 years ago

0 David (ASIC) Liu over 7 years ago

TI__Guru**** 186751 points

Jon

Are they seeing good output on all four lanes but not seeing the sync packet, or they are seeing good output only on lane 0?

Thanks
David

0 Jon Key over 7 years ago in reply to David (ASIC) Liu

TI__Intellectual 920 points

Hi David,

They are seeing good output on all lanes from an SI standpoint, but are only seeing sync packets on lane 0.

Thank you,

Jon

0 David (ASIC) Liu over 7 years ago in reply to Jon Key

TI__Guru**** 186751 points

Jon

What is the skew between the clock and lane 0-3?

I am wondering if they violate the setup/hold timing between the clock and lane 1-3 (if the skew exceeds the spec) that the sync packet is not being mis-sampled.

But DPHY440SS will not filter out the sync packet.

Thanks
David

Interface

Interface forum

SN65DPHY440SS: Missing sync packets and changing LP-HS transition time