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DS90UB953-Q1: Strap Configuration Mode Select

Tomoaki Yoshida91
Genius 5255 points
Part Number: DS90UB953-Q1

Hi team,

I have some questions about strap configuration mode select.

The 953 datasheet has been updated recently, and it seems that the recommended resistance value for mode selection has been changed.

#1

Could you tell me the reason why the recommended resistance value has changed?

#2

My customer set the resistance according to the previous datasheet, but is there a problem in use?

Could you tell me if there is any impact?

#3

They will design a datarate of 3.6 Gbps in the future.

I think that there are two setting methods in Non-synchronous external clock mode.

 No.1 : CLKIN DIV=1    FC DATA rate   f*80

 No.2 : CLKIN DIV=2    FC DATA rate   f*40

Could you tell me the difference between the two and which one should they choose?

Best regards,

Tomoaki Yoshida

  • 0
    TI__Genius 11340 points

    Hi Yoshida-san,

    Please refer to my comments below:

    #1

    Could you tell me the reason why the recommended resistance value has changed? These values are just suggested values. 

    #2

    My customer set the resistance according to the previous datasheet, but is there a problem in use? There shouldn't be any problems using the resistance values from the previous datasheet. The voltage divider ratio is still the same.

    #3

    They will design a datarate of 3.6 Gbps in the future.

    I think that there are two setting methods in Non-synchronous external clock mode.

     No.1 : CLKIN DIV=1    FC DATA rate   f*80

     No.2 : CLKIN DIV=2    FC DATA rate   f*40

    Could you tell me the difference between the two and which one should they choose? 

    This would depend on your reference clock frequency and your desired forward channel rate. For example, if you want your forward channel rate to be 4Gbps, you could set your CLKIN_DIV = 1 and use a 50MHz clock, or you could set your CLKIN_DIV = 2 and use a 100MHz clock.

    Best,

    Jiashow

  • 0 in reply to Jiashow Ho
    Genius 5255 points

    Hi Jiashow-san,

    Thank you for your support.

    I understand your answers.

    I have more question for #3.

    Is there no functional difference other than CLK_DIV?

    Which one should use ref clk 50 MHz, 100 MHz for 4Gbps?

    I want to know what to consider, such as the effect on noise.

    Best regards,

    Tomoaki Yoshida

  • 0 in reply to Tomoaki Yoshida91
    TI__Genius 11340 points
    Hi Yoshida-san,

    Both should work, but if you can use 50MHz , use it instead of 100MHz. Every time you have a multiplier/divider to the clock, you might be introducing some jitter to the system.

    Best,
    Jiashow