Hi Sirs,
Sorry to bother you.
Could you check our schematic again?
Any suggestion are welcome.
Thanks!!
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Hi Sirs,
Sorry to bother you.
Could you check our schematic again?
Any suggestion are welcome.
Thanks!!
Hi David,
Please refer our update as below
1. What is being connected to U3_USB_SSRX1_N/P?
We have one carrier board and IO board, the USB 3.1 GEN2 connector on IO board, so I add GEN2 re-driver on my carrier, the carrier board and IO board connected by board to
board connector, but I have one question, if I add this re-driver on IO board, do you have any suggestion on this case?
2. Where are the AC coupling caps for RX2 and TX2?
I add AC coupling caps of RX on conn side, the TX AC coupling caps on IC side, is this OK for this design?
3. May consider change one 0.1uF to 1uF for the 3.3V supply.
OK
4. One more thing need confirm, I saw SLP_S0# (pin 14) should be connected to a GPIO that indicates the system sleep state. If the system SoC does not support this option, then it is recommended to leave this pin unconnected. So we will connected to S4 signal, how about this signal is ok?