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DP83620: Basic configuration with MDIO Interface for TX mode

Part Number: DP83620


Could you anyone point the configuration Note for 100BASE-T ?

Need an basic initialization routine.

Vrai

  • Hello Vrai,

    What basic initialization are you looking for? The PHY will power up in default MII mode with autonegotiation ON. Certain modes of the PHY are controlled via bootstrap resistors which gives customer the option to change the default power up modes. Advanced feature can be controlled via register access.

    -Regards,
    Aniruddha
  • Hi Aniruddha

    It seems that the default might be working for MII mode with auto-negotiation On.

    I just need to test an TX mode only in a MAC Controller 10Mhz or 100Mhz.

    would you suggest how to work with the PHY chip?

    Simply I am trying to send TX_CLK, TX_EN, TXD[3:0] to DP83620 without MDIO/MDC interface to control registers.(Not ready the MDIO Interface yet and do not know how to control as minimum setting)

    Another question is the MAC Header data is generated 32bit  as following 802.3 standard, but DP83620 has 4bit data width.

    The data width can bed reduced to 4bit from 32bit, Do you have a bit ordering format in the PHY Chip?

     

    the last question is 

    If the default is set to 100BASE-T, Should the TX_CLK be exactly 25Mhz ? if TX_clk is less 25Mhz, will it acceptable to DP83620?

    I am also wondering if the default is working for power enable, any required reset state, default mode and speed, I would want to know details?

    I appreciate any comments in advance.

    Regards vrai 

     

     

  • Hi Vrai,

    The PHY will need to be connected to a link partner over Cat5e cable in order to have a successful link up. If the link is at 10Mbps, then MII will be 2.5MHz and if link is 100Mbps then MII will work at 25MHz. This happens automatically. The MII clock speed is defined by standard for each data rate so if 100Mbps link up is needed, MII has to work at 25MHz. The default mode on power on is to have autonegotiation on, Auto-MDIX on, MII mode. Of course these can be changed via external bootstrapping resistors or software registers.
    If ethernet MAC that you are usingis verified for MII operation, then the clocking data over TXD[3:0] is handled internal to MAC and PHY. However, if you are planning to create your own MAC implementation I would recommend reviewing the IEEE 802.3 standards for MII and Ethernet MAC.

    -Regards,
    Aniruddha
  • Hi Aniruddha

    Thank you for this following post. I appreciate it.

    Could you elaborate on what is the default Speed in MII mode after just power-on  in case of no register Control through MDIO?

    Is there an external resistor for this speed selection?

    Regards Vrai

  • Hi Aniruddha

    Thank you for this following post. I appreciate it.

    Could you elaborate on what is the default Speed in MII mode after just power-on  in case of no register Control through MDIO?

    Is there an external resistor for this speed selection?

    I am trying to write RTL Codes in FPGA for this MAC Control, so would want to know the Initial PHY Status.

    Regards Vrai

  • Hi Vrai,

    After power on there is no default speed, both 100Mbps and 10Mbps will be advertised. Based on the auto-negotiation process, either 10 or 100Mbps link will be resolved. The speed can be fixed externally by using strapping resistors. Please refer to the Strap Options section of the datasheet for information on how to disable auto-negotiation and fix the speed.

    -Regards
    Aniruddha