Could you anyone point the configuration Note for 100BASE-T ?
Need an basic initialization routine.
Vrai
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Could you anyone point the configuration Note for 100BASE-T ?
Need an basic initialization routine.
Vrai
Hi Aniruddha
It seems that the default might be working for MII mode with auto-negotiation On.
I just need to test an TX mode only in a MAC Controller 10Mhz or 100Mhz.
would you suggest how to work with the PHY chip?
Simply I am trying to send TX_CLK, TX_EN, TXD[3:0] to DP83620 without MDIO/MDC interface to control registers.(Not ready the MDIO Interface yet and do not know how to control as minimum setting)
Another question is the MAC Header data is generated 32bit as following 802.3 standard, but DP83620 has 4bit data width.
The data width can bed reduced to 4bit from 32bit, Do you have a bit ordering format in the PHY Chip?
the last question is
If the default is set to 100BASE-T, Should the TX_CLK be exactly 25Mhz ? if TX_clk is less 25Mhz, will it acceptable to DP83620?
I am also wondering if the default is working for power enable, any required reset state, default mode and speed, I would want to know details?
I appreciate any comments in advance.
Regards vrai
Hi Aniruddha
Thank you for this following post. I appreciate it.
Could you elaborate on what is the default Speed in MII mode after just power-on in case of no register Control through MDIO?
Is there an external resistor for this speed selection?
Regards Vrai
Hi Aniruddha
Thank you for this following post. I appreciate it.
Could you elaborate on what is the default Speed in MII mode after just power-on in case of no register Control through MDIO?
Is there an external resistor for this speed selection?
I am trying to write RTL Codes in FPGA for this MAC Control, so would want to know the Initial PHY Status.
Regards Vrai