PCA9546A: Vpass MIN MAX explanation

Hey Pengfei,

I think there may be a misunderstanding as to what Vpass is and how to choose Vcc based on Vpass.

"Vpass voltage must be equal to or lower than the lowest bus voltage" Vpass is defined in our datasheet as the lowest pull up voltage on the channels (main channel included) but can be chosen as something lower.

"Why do we have to limit Vpass lower than lowest bus voltage? " You do not need to choose a lower voltage than Vpass but choosing a lower Vpass forces you to choose a lower Vcc for the device.

"What is it about the Internal detailed logic circuit？"

This device uses a pass FET architecture. In order to pass a low you need the Vgs to be greater than Vth.

"Could you explain why the Vpass is lower than lowest bus voltage?"

If you choose a lower Vpass then the Max Vcc for the device goes lower. The Vpass is used as a definition solely for the purpose of using figure 11 in the datasheet.  For example, if 2.7V is the lowest voltage on the bus then Vpass is 2.7V or lower. Chart 11 states that if I used 2.7V as the Vpass then my Vcc for PCA9548A MUST be 4V or lower (I could use Vcc as 3.3V for example) but I cannot exceed 4V (I'm using the typical curve in green).

Think about this in the sense of a passFET where Vcc feeds into the gate.

If Vth is 1.3V @ Vcc=4V and my pull up voltage on one side of the bus is 5V for example but 2.7V on the other side then Vgs is 4V-2.7V which is 1.3V which is NOT greater than Vth so the two sides are high impedance (open switch) in this case my device keeps 2.7V seperated from 5V.

Now lets say I choose Vcc=5V for my Vcc of PCA9548A and I still have a 2.7V bus and a 5V bus. This means the Vgs is 5V-2.7V which is 2.3V. 2.3V is greater than the Vth which in my last example was 1.3V. This means the impedance between the 5V bus and the 2.7V bus is no longer high impedance but instead low impedance (closed switch) so the two buses are no longer isolated.

Now in this last example, My lowest bus voltage will be 2.7V like before but instead I choose Vcc=3.3V because Vpass =2.7V or lower, I pick Vcc to be 4V or less (3.3V is less in this case). So the Vgs in this case is 3.3V-2.7V which is 0.6V. 0.6V is less than 1.3V (The Vth we decided to stick with). The two buses are seperated because the FET is acting in the cut off region.

I prove this in simulation here:

I hope this makes sense to you. If you have further questions, I'd be happy to address them.

Thanks,

-Bobby