LMH1297: Lock Data Rate Indication not always correct.

Tonnie Wittenaar

Part Number: LMH1297

Hi,

We have developed a Fiber converter and now production has started the client wants the actual lock data rate be displayed.

While the hardware locks fine to the signal and the output is very clean measured on a 12G measurement device. I get very often a wrong data rate back when running the Lock Data Rate Indication procedure (Programming guide 3.11)

Most of the times it goes bad at the point the SDI cable is still connected to the converter, and we change the SDI rate in the generators. But it happens too when plug a cable from a reset state.

So i'm trying to find my fault in the process, And i'm wondering if i'm doing something wrong in to initiate / reinitiate when lock is detected.

While SDI lock goes down we run a CDR Reset, As we have found that the CDR might keep the old settings of the previous signal if we do not apply a CDR reset when lock has gone.

When lock is lost, we start looping till we have a Carrier Detect and we perform a InitEQ or InitCD (Depending if it is an input or output) . (3.1.1 / 3.1.2)
After a stable lock we probe for the Lock Datarate (3.11) But we often get 6G indication with 1,5G input, or 1,5G indication when 12G input. But it is a bit random, it might indicate 5 times in a row ok.. And then 2 times miss it.

We also tried with do a full CTLE/CDR register reset and restore defaults, But that does change a lot, but takes more time to relock.

So What is the best procedure when lock is lost and relock to a different signal. ( would be nice if there was a writen step plan or flow diagram to set the LMH1297 in the proper state to relock to a new signal when signal is lost.

The weird thing is that the output sdi signal looks good, So the CDR seems to lock proper to the signal but the indication is off..

As generators we use BMD Teranex AV, Atem 1M/E 4K and a Phabrix QX12G All with the same results.

over 6 years ago

0 Nasser Mohammadi over 6 years ago

TI__Guru* 93670 points

Hi Tonnie,
The fact device is locked and data is going through with no bit errors, this means device is locked at the right data rate and lock rate indication should be fine as well. Otherwise you would be getting bit errors

Procedure or written steps or flow diagram to set the device in proper state: Procedure is very simple, do nothing. When signal gets lost, device state machine restarts - so there is no need for retimer reset. A retime or CDR reset would not have a negative side effect - as far as i can see - but it is not needed. You can just monitor lock indication or setup the device to cause interrupt when there is a lock or loss of lock and then read the status. Please note section 3.16.7 of the LMH1297 programming guide for further details.

I think it is possible that problem you are describing maybe is coming from the procedure to read data rate indication. Below are the steps in the programming guide - as you pointed out:
1. RAW FF 04 07
2. RAW 0C 00 F0
3. RAR 02 18 18
4. RAW 0C 30 F0
5. RAR 02 38 38
6. RAW 0C 00 F0
Step #2 is what could be causing the issue you are describing. In this step we are just writing into higher nibble of the reg 0x0C. If you write into lower nibble then you could be falling into the situation you described. So in general please make sure you write into the register bits noted in the mask setting as "1".

Please let me know if this helps.

Regards,,nasser

0 Tonnie Wittenaar over 6 years ago in reply to Nasser Mohammadi

Prodigy 50 points

Hi Nasser,

Thanks for the answer, I was so focused on what could be set wrong for the state machine to run correct that i had not saw a flaw in the bitmask routine to add the new data to the exciting read back from the register.

So i made some debug to fix that issue. But my main issue is still present. For example the debug now says 12G-SDI while the signal send into the converter is a proper 6G-SDI 3840x2160P25 YCbCr 422 2-SI Rec.709 Signal from a Phabrix QX 12G.

Also in my ReadData for 0x0C After reg 0x02, The value read back is always 0. So at this point there seems to be no data into the lower nible of 0x0C. But at least i fixed my code to apply the Mask and data correct.

Is there any other registers i can check to see proper lock or errors? To see if this might give more insight of what could be going on here.

Just tested, needed to disconnect the fiber line 4 times before it finally sayed Lock 6G. The other times it was 12G and unlocked if the fiber was removed.

Start Lock Data Rate indication

   Register 0xFF
   ReadData 00000100
            Mask 00000111
           Value 00000100
          outVal 00000100

   Register 0x0C
   ReadData 00000000
             Mask 11110000
            Value 00000000
           outVal 00000000

        Read Register 0x02 01011000
SDI B > Lock register SDI  01011000 58  == Lock SDI 
   Register 0x0C
   ReadData 00000000
             Mask 11110000
            Value 00110000
           outVal 00110000


      Read Register 0x02 10000000
      Rate register SDI  10000000      Rate register after mask  0  12G-SDI

   Register 0x0C
   ReadData 00110000
             Mask 11110000
            Value 00000000
           outVal 00000000
Lock Data Rate indication done

0 Nasser Mohammadi over 6 years ago in reply to Tonnie Wittenaar

TI__Guru* 93670 points

Hi Tonnie,

You said you are using 3840X2160p25.

Is the video going through without error even though device says this is 6G

Regards,,nasser

0 Tonnie Wittenaar over 6 years ago in reply to Nasser Mohammadi

Prodigy 50 points

Hi Nasser,

The lmh1297 gives status of 12G while running 6G trough. But it also happens to idicate at random. So the next time i plug it could indicate 3G or 1,5G or gives me exact the 6G as indication. That is why i put the question up. The Phabrix reports a clean output signal without errors, crc issues and a nice clean eye with about 0.08Ui jitter in 100Khz at 6G-sdi

So i was wondering if there are undocumented registers we could read out, that might reveal what is happening.
Or i send the code after the weekend by email for review? To determine if something is setup wrong?

Regards, Tonnie

0 Nasser Mohammadi over 6 years ago in reply to Tonnie Wittenaar

TI__Guru* 93670 points

Hi Tonnie,

The fact Phabrix is reporting a clean output eye diagram without errors, this indicates device has locked at the right rate. Once device is locked at the right rate, it would indicate correct data rate settings - else you would get constant bit error.

I checked your programming steps and did not find anything wrong. Before we read rate indication, we check to make sure device is locked. As an experiment, please put a wait state for 20ms before you read rate indication. Under this condition, do you see wrong rate indicator?

Secondly, the fact device is running without error it means device is locked at the right rate and rate indication - if read properly - should have the right value. Otherwise, you would get constant bit error. Please check your programming step to make sure you are indeed compiling with the programming guide register settings.

Regards,,nasser

Interface

Interface forum

LMH1297: Lock Data Rate Indication not always correct.