DS90UB947-Q1: Register Setting guidance

Hello,
The setup of the Serializer and Deserializer are done in pairs. I try to draw a block diagram, and record the features needed, and inclock.

The order of a-e is not important but they are needed before programming, check detailed description and application in datasheet

note: not a programming task, but power sequence, PDB must be done per datasheet, there is no software fix for errors in this.

a) Mode of operation strapping - Check Model Select for both devices
check 8.4 in the datasheet, if there is a choice of Single or Dual OLDI - suggest starting with Single OLDI
Serializer / Deserializer pair, vs repeater which has more parts (check HDCP Application note for repeater application)
Table 6,7,8 has general categories and resistor strapping
Check Register 2 to make sure the strap value is OK

b) I2C communication IDX strapping - range of I2C addresses
Table 9
always check the desired I2C Device ID, register0, if it doesn't search for which I2C block is selected in IDX

c) depending on the desired communication method
IVI example - SOC <-> I2C <-> Serializer <-> FPDLink <-> Deserializer <-> I2C <-> Display
see FPDLink I2C Application note
c1) based on strapping and figure, determine the desired Deserializer I2C IDX address, and Deserializer I2C Slave addresses
c2) determine the Alias address you would like to program for the remote Deserializer Alias I2C, and the remote Deserializer I2C Slave Alias
c3) check that one set of pullup resistors is applied for each I2C bus on the Deserializer / Serializer pins

d) number of input, output main signals select - and check default or reg bits

e) clock method , other IO INTB, REMINTB, GPIO - you need to figure out your uses of pins, and if you need to forward GPIO from Ser -> Deser or Seser -> Ser. Follow sections in datasheet, then setup programming

f) there are programmed default values, these can be checked if other registers need to be changed, simple 24bit modes may work
with no reprogramming, if you need a non default feature, then you need programming
Note: reserved value bits should be left as power on default
Note: some devices have an Errata - this is needed for certain conditions, these need to be requested
Note: registers are in decimal, if its not liisted, use default value or ask additional questions

Reg 1 - resets can be reprogrammed but not required

Reg4 - Mode Select - special controls (bit 4 is used in some Errata programming)
reg19 - should match mode strapping, can be changed in software, check description in datasheet
reg18, data path control - match desired feature with description in datasheet
reg26, 28bit mode, I2S features
reg32 - additional mode feautres
reg 79 - bridge ctl - additional repeater mode controls
reg 84, 85, 87 - additional I2S controls
reg 91 - Dual_CTL1 - dual mode, coax/STP
reg 92 - Dual_CTL2 - additional dual controls
reg 194 - repeater controls

Reg 6 - normally copied from Back channel, from Serializer (can check value)
reg 7 - you must program the I2C Slave ID at the Serializer to recognize this I2C to forward
reg8 - Remote I2C Slave address used (reg7 is SOC side, reg 8 is I2C side)
reg21 - prefer I2C voltage of 3.3v, can be changed and monitored

reg112 - 125 - remote Deserializer Slave address/Alias from the Serializer Local I2C

note: remember that bit forwarding needs an input on the source side, and the destination is not programmable, it follows the source
reg13 - (special POST1_SEL sequence bit - GPIO0 D_GPIO0, needs to follow the use
reg14 - (special POST1_SEL sequence bit - GPIO1,2 D_GPIO1,2, needs to follow the use
reg15 - (special POST1_SEL sequence bit - GPIO1,2 D_GPIO1,2, needs to follow the use
reg16,17 GPIO5-8 IO programming
reg30 has the I2C Port Select

reg20 - BIST Control - needs to be coordinated with deserializer
reg27 BIST Back channel error counter (write to clear)

reg 72, 73, 75 are used for indirect I2C Serializer registers in Errata procedures - not programmed normally

reg23.24.25 - advanced I2C controls, normally not changed

reg 96, 97, 98 - SPI Controls on the D_GPIOx if needed

reg 100-103 - Pattern Generator Indirect control (see Pattern Generator app note)

g) there are status registers which are programmed to clear

Regards,
Joe Quintal

Hello,
The 100Mhz equivalent LVDS input, is done by using Dual Link 50Mhz clock input.
The Single OLDI limit is 96Mhz
Regards,
Joe Quintal