DP83822I: RESET_N pull-up/down; XI applied after Vddio & Vavd

KKF

Part Number: DP83822I

Hi,

Does RESET_N pin have a 9kOhm internal pull-up?
Can you confirm there is no issue when XI clock is applied to DP83822 after the ramp up of the supply voltages?

Thanks a lot in advance & BR,
KF

over 6 years ago

0 Geet Modi over 6 years ago

TI__Mastermind 26320 points

Hi,

1. Yes, DP83822 has integrated POR and internal PU of 9K.

2. Clock is needed at POR as shown in POR timing diagram for DP83822.

Regards,
Geet

0 Geet Modi over 6 years ago in reply to Geet Modi

TI__Mastermind 26320 points

Hi,

I am closing this thread. Incase you have further queries, please open new thread and provide reference to this thread.

Regards,
Geet

0 Geet Modi over 6 years ago in reply to Geet Modi

TI__Mastermind 26320 points

Just to further clarify if clock is delayed at POR, then additional reset is needed on DP83822.

For example :
1. Vdd applied to the PHY first,
2. Clock is provided on XI to the PHY,
3. Release the reset after PHY has seen stable XI for sufficient amount of time :

This sequence is acceptable for DP83822.

Clock at POR is needed when host is not controlling the resets.

Regards,
Geet

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DP83822I: RESET_N pull-up/down; XI applied after Vddio & Vavd