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DS90UB926Q-Q1: What impact if power up sequence is violated

Soichi Nishimura
Expert 5165 points
Part Number: DS90UB926Q-Q1

Hi team,

Our customer has a question to DS90UB926Q1.

In their system, it seems they violate power up sequence of VDDIO. The dataseet of DS90UB926 requires VDDIO rump must be faster than 1.5ms. But they rump VDDIO in 4.8ms.

Customer wants to know what impact when VDDIO sequence is violated.
Could you tell me the reason why the device required VDDIO sequence and what impact to device if VDDIO sequence is violated?

Regards,
Nishimura

  • 0
    TI__Mastermind 37500 points

    Hello,

    The device operation is not guaranteed by design, if the Power Sequence or Power Ramp does not meet the section 9.1 requirements.  

    Customers can have problems, with strapping controls even if PDB is released later..

        Improper Mode Select - given the strapped voltage (can be overriden in software)

        Improper IDX - I2C selection (you can search for the base I2C address)

        the device may not initialize when PDB is released (this is the primary concern)

     Section 9.1 in the DS90Ux926 datasheet, listed VDDIO first, a gaptime, then VDD33_X.  Both supplies are supposed to take < 1.5ms.

    Using PDB from a micro controller instead of an RC network allows for Errata sequences to include the external reset.

     Note: as a suggestion, incorporating a load switch in the design, you can enforce a sequence, and only connect the power rail to the device, when its at the desired voltage, this allows the device to see a faster voltage transition.  One customer recently found that the Soft Start capacitor on their power design, could be reoptimized to meet the dvdt requirement.

    Regards,

    Joe QUintal

  • 0 in reply to Radio-Joe
    TI__Expert 5165 points

    Hi Joe,

    Could you tell me more information to the issue in case of VDDIO sequence violation?

    Customer is just facing the trouble of I2C address issue as you mentioned. So, customer asked us to confirm detail to this issue. Customer thinks it's necessary to confirm the trouble is coming from this VDDIO sequence vilolation.

    1) Is the I2C issue replicable by device? If one device was occurred improper I2C address by 4.8ms rump time, the device always occur improper address again under same condition, is my understanding correct? Or, is it possibility to not happen the improper I2C address under same condition?


    2) The datasheet requires VDDIO rump faster than 1.5ms. Is it possibility to not happen the improper address issue even if the VDDIO rump slower than 1.5ms? How long rump time require if improper I2C address issue must be triggered?

    Regards,
    Nishimura

  • 0 in reply to Soichi Nishimura
    TI__Mastermind 37500 points

    Hello,

    There are analog circuits that initialize while the VDDIO and VDD are ramping.   A portion of this circuitry is the MODE SELECT strapping, and the IDX strapping.

    Each device has a part variation, some parts are more sensitive.  The 1.5ms power ramp was specified so that all devices would meet the proper operation.

    The MODE SELECT has I2C bits which can be programmed, after digital reset PDB is released.   The IDX can be reassigned, but you need to know which base I2C address is present.

    The customer must fix the power ramp for reliable operation.  The above description are software methods that can help stabilize the design.

    Regards,

    Joe Quintal