HD3SS3412: Question about routing

Roy Hsu

Part Number: HD3SS3412

Hi Team,

My customer plans to use our HD3SS3412 in a project and the application is shown as below. I am still trying to figure out why they need two stages of multiplexer.

1. For channel A (upper one), 3 of the differential pairs are routed to the golden finger directly. Since HD3SS3412 introduces 1.5 dB of insertion loss, which means that the loss profile is not identical among the 4 differential pairs. That said, do they need to create an 1.5 dB loss in the traces of the 3 differential pairs on purpose for the loss profile to match among the 4 differential pairs?

2. For channel B (lower one), 3 of the differential pairs go through two stages of mux. Is there any concern on this?

Thanks!

Roy Hsu

over 6 years ago

0 Lee Sledjeski over 6 years ago

TI__Mastermind 43795 points

Hi Roy,

There is some concern. Often adjacent lanes are grouped together in bundles by the processor. They do this to share information about equalization settings. I would try to compensate by adding loss to the non-mux channels. It may be possible to alter the trace width and pair separation distances to acheive higher loss without having to add so much length to the traces.

Regards,

Lee

0 Roy Hsu over 6 years ago in reply to Lee Sledjeski

TI__Genius 9350 points

Hi Lee,

To compensate by adding loss to the non-mux channels, do we need to consider both the insertion loss and propagation delay?

Thanks!

Roy Hsu

0 Lee Sledjeski over 6 years ago in reply to Roy Hsu

TI__Mastermind 43795 points

Hi Roy,

The primary concern is the insertion loss. The propagation delay differences will still be orders of magnitude below the PCIe specification for lane-lane skew.

Regards,

Lee

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HD3SS3412: Question about routing