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Serdes solution recommendation for general purpose data

Other Parts Discussed in Thread: DS32EL0421

Team, 

Please provide some guidance on best solution to recommend for: 

We are looking for serializer (and matching deserializers) to serialize general purpose data. When we searched through TI offering, DS32EL0421 is the one of chips of interest. But there are lot more options with FPD link serializer. 

 Our requirements (with some embedded questions) are:

  1. Single ended general purpose parallel bus. Nibble wide interface is preferred but byte wide is ok.
  2. SDR or DDR interface
  3. LVDS is as fine as LVCMOS
  4. serialized bandwidth of about 800 Mbps but it should be capable of supporting more bandwidth as high as 2 gbps or so if we need to expand it in future. For example, I am guessing that we can operate even single lane of DS32EL0421 LVDS input and getting us the lowest throughput with lowest power. As bandwidth requirement increases, we can add more LVDS inputs. Is that possible with DS32EL0421 or such devices?

Questions:

  1. Shall we use FPD link serializer for chip to chip communication on PCB? Will this be more power hungry than DS32EL0421?
  2. Can FPD link serializer automatically reduce its power consumption when connecting to deserializer which are connected over PCB back plane (not going through STP cable but from one plug-in-module to another plug-in-module on mother board, so going through 4 connectors for like 5 to 10 inch of PCB traces)
  3. Using FPD link serializer and deserilzer from PCB to another PCB through connectors is one of allowed ways to use the FPD link Serdes
  4. What is the minimum required PCB trace length between FDP link serializer and deserializer? For example, Would 5 Inch cause too much over shoot and undershoot on the signals?
  5. Are there any app note that talks about selection of connectors for carrying FPD link signals?

  6. What are TI's recommendation for chip to chip communication?
  7. As far as I have seen, all the FPD link serializers are made for camera input. Shall we tie HSYC and Vsync to constant values and use the single ended data bits (any where between 4 to 10 bits) to transfer the data? Is it a recommended use if camera is not feeding the data?
  8. Could you give me list of devices like DS32EL0421?
  9. Any other better way to serialize data from general purpose FPGA?

Thanks

Viktorija

  • Hi Viktorija,

    If your bandwidth requirement increases you can implement link-aggregation to expand the bandwidth up to 5 Gbps using 2x DS32EL0421/0124. You can reference this application note for more details: www.ti.com/.../snla109a.pdf

    The FPD-Link II/III are similar to the DS32EL0421, and it looks like you're already familiar with the devices in these categories. You can find them in the parametric search:
    www.ti.com/.../products.html

    For serializing FPGA data either the DS32EL0421 or FPD-Link is the best way. The DS32EL0421 is an FPGA-Link Serializer and was designed to be FPGA friendly.

    It looks like the rest of your questions are FPD-Link oriented so I will go ahead and move this thread to the FPD-Link section for further discussion.

    Regards,
    I.K.
  • Hello,

    Considering FPDLink3 devices, you have 24bit RGB parallel LvCMOS, or 4 LVDS lane OLDI with 7 data bits per LVDS lane.

      - FPDLink RGB888, with small CPLD.  - you could directly sample LvCMOS and transfer this over FPDLink.

           a) you need to make sure the devices used have compatibility 9(odd)(odd) is a serializer.  9(odd)(even)  is a deserializer.

                913A - 914A

                 transfer 12 LvCMOS bits at 75Mhz

                 transfer 6 LVCMOS bits , with 1:2 CPLD at 150Mhz 2:1 CPLD on deserializer side

                933 - 934

                 transfer 12 LvCMOS bits at 100Mhz

                 transfer 6 LVCMOS bits , with 1:2 CPLD at 200Mhz (special deskew); also 1:2 CPLD on deserializer side, with specialized clock skew 200Mhz

           b) 921 - 926

                 transfer  27 LvCMOS bits at  85Mhz

                 transfer 13 data bits and clock, with 1:2 CPLD at 170Mhz, and 2:1 Mhz with clock skew at 170Mhz

           note: there are LVDS devices, but these utilize a special clock format OLDI

         LVDS would be simpler with non FPDLink parts, FPDLink requires 7:1 serialization and special clock.

    Regards,

    Joe Quintal