Other Parts Discussed in Thread: TEST2
Hi,
My customer meets an issue about SN65DSI186, could you please help me solve this problem? Thanks.
There are two Dell DP, and the timing parameter is the same, but just one can be lightened.
1、Dell SP2318H lightened, EDID,timing and DPCD are:
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Dump Panel EDID
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00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
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00| 00 ff ff ff ff ff ff 00 10 ac fc a0 53 47 41 32
10| 02 1c 01 04 a5 33 1d 78 3a eb f5 a6 56 51 9c 26
20| 10 50 54 a5 4b 00 71 4f 81 80 a9 c0 d1 c0 01 01
30| 01 01 01 01 01 01 02 3a 80 18 71 38 2d 40 58 2c
40| 45 00 fd 1e 11 00 00 1e 00 00 00 ff 00 34 30 44
50| 34 57 38 31 42 32 41 47 53 0a 00 00 00 fc 00 44
60| 45 4c 4c 20 53 50 32 33 31 38 48 0a 00 00 00 fd
70| 00 38 4c 1e 53 11 01 0a 20 20 20 20 20 20 00 c2
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Extract Panel timing from EDID
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Pixel Clock : 148500 KHz
XDOT * YDOT : 1920 * 1080
HPW * VPW : 44 * 5
HBP * VBP : 148 * 36
HFP * VFP : 88 * 4
HSYNC: Positive
VSYNC: Positive
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Dump Panel DPCD Value
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0000h: 11 0a 84 01 01 00 01 00 02 02 06 00 00 00 00 00
0100h: 06 04 00 00 00 00 00 00 01 04 00 00 00 00 00 00
0200h: 01 00 77 11 80 00 00 00 00 00 00 00 00 00 00 00
0210h: ff 7f ff 7f ff 7f ff 7f 10 0a 00 00 00 00 00 00
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DPCD: REV:1.1
MAX_LINK_RATE:2.7Gbps
MAX_LINK_LANE:4
Not support ASSR
Not support Enhance framing
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2、Dell P2314H can not be lightened, EDID,timing and DPCD are:
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Dump Panel EDID
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00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
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00| 00 ff ff ff ff ff ff 00 10 ac 98 40 4c 57 44 42
10| 1f 19 01 04 a5 33 1d 78 3a e5 95 a6 56 52 9d 27
20| 10 50 54 a5 4b 00 71 4f 81 80 a9 c0 d1 c0 01 01
30| 01 01 01 01 01 01 02 3a 80 18 71 38 2d 40 58 2c
40| 45 00 fd 1e 11 00 00 1e 00 00 00 ff 00 48 4d 4a
50| 31 56 35 38 31 42 44 57 4c 0a 00 00 00 fc 00 44
60| 45 4c 4c 20 50 32 33 31 34 48 0a 20 00 00 00 fd
70| 00 38 4c 1e 53 11 01 0a 20 20 20 20 20 20 00 a8
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Extract Panel timing from EDID
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Pixel Clock : 148500 KHz
XDOT * YDOT : 1920 * 1080
HPW * VPW : 44 * 5
HBP * VBP : 148 * 36
HFP * VFP : 88 * 4
HSYNC: Positive
VSYNC: Positive
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Dump Panel DPCD Value
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0000h: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00 00
0100h: 0a 82 00 00 00 00 00 00 00 00 0b 00 00 00 00 00
0200h: 41 00 77 00 01 00 00 00 00 00 00 00 00 00 00 00
0210h: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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DPCD: REV:1.1
MAX_LINK_RATE:2.7Gbps
MAX_LINK_LANE:4
Not support ASSR
Not support Enhance framing
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please see the attached files for more details.
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Dump Panel EDID
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00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
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00| 00 ff ff ff ff ff ff 00 10 ac 98 40 4c 57 44 42
10| 1f 19 01 04 a5 33 1d 78 3a e5 95 a6 56 52 9d 27
20| 10 50 54 a5 4b 00 71 4f 81 80 a9 c0 d1 c0 01 01
30| 01 01 01 01 01 01 02 3a 80 18 71 38 2d 40 58 2c
40| 45 00 fd 1e 11 00 00 1e 00 00 00 ff 00 48 4d 4a
50| 31 56 35 38 31 42 44 57 4c 0a 00 00 00 fc 00 44
60| 45 4c 4c 20 50 32 33 31 34 48 0a 20 00 00 00 fd
70| 00 38 4c 1e 53 11 01 0a 20 20 20 20 20 20 00 a8
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Extract Panel timing from EDID
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Pixel Clock : 148500 KHz
XDOT * YDOT : 1920 * 1080
HPW * VPW : 44 * 5
HBP * VBP : 148 * 36
HFP * VFP : 88 * 4
HSYNC: Positive
VSYNC: Positive
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Dump Panel DPCD Value
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0000h: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00 00
0100h: 0a 82 00 00 00 00 00 00 00 00 0b 00 00 00 00 00
0200h: 41 00 77 00 01 00 00 00 00 00 00 00 00 00 00 00
0210h: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
------------------------------------------------------
DPCD: REV:1.1
MAX_LINK_RATE:2.7Gbps
MAX_LINK_LANE:4
Not support ASSR
Not support Enhance framing
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--------------------------------------------------
Dump Panel EDID
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00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
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00| 00 ff ff ff ff ff ff 00 10 ac fc a0 53 47 41 32
10| 02 1c 01 04 a5 33 1d 78 3a eb f5 a6 56 51 9c 26
20| 10 50 54 a5 4b 00 71 4f 81 80 a9 c0 d1 c0 01 01
30| 01 01 01 01 01 01 02 3a 80 18 71 38 2d 40 58 2c
40| 45 00 fd 1e 11 00 00 1e 00 00 00 ff 00 34 30 44
50| 34 57 38 31 42 32 41 47 53 0a 00 00 00 fc 00 44
60| 45 4c 4c 20 53 50 32 33 31 38 48 0a 00 00 00 fd
70| 00 38 4c 1e 53 11 01 0a 20 20 20 20 20 20 00 c2
------------------------------------------------------
Extract Panel timing from EDID
------------------------------------------------------
Pixel Clock : 148500 KHz
XDOT * YDOT : 1920 * 1080
HPW * VPW : 44 * 5
HBP * VBP : 148 * 36
HFP * VFP : 88 * 4
HSYNC: Positive
VSYNC: Positive
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Dump Panel DPCD Value
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0000h: 11 0a 84 01 01 00 01 00 02 02 06 00 00 00 00 00
0100h: 06 04 00 00 00 00 00 00 01 04 00 00 00 00 00 00
0200h: 01 00 77 11 80 00 00 00 00 00 00 00 00 00 00 00
0210h: ff 7f ff 7f ff 7f ff 7f 10 0a 00 00 00 00 00 00
------------------------------------------------------
DPCD: REV:1.1
MAX_LINK_RATE:2.7Gbps
MAX_LINK_LANE:4
Not support ASSR
Not support Enhance framing
------------------------------------------------------
void SN65DSI86_Init(void)
{
u8 buf[2];
MIPI2DP_RST_L;
Delay_ms(20);
MIPI2DP_RST_H;
Delay_ms(20);
MIPI2DP_Write(0x09, 1, 0x01);
Delay_ms(20);
MIPI2DP_Write(0x09, 1, 0x00);
Delay_ms(20);
if(isDual)
{
MIPI2DP_Write(0x0A, 1, 0x06); //REFCLK 27MHz
MIPI2DP_Write(0x10, 1, 0x80); //Dual(Left & Right) 4 DSI lanes
MIPI2DP_Write(0x12, 1, 0x32); //DSIA CLK FREQ 222MHz
MIPI2DP_Write(0x13, 1, 0x32); //DSIB CLK FREQ 222MHz
MIPI2DP_Write(0x94, 1, 0x80); //HBR (2.7Gbps)
MIPI2DP_Write(0x0D, 1, 0x01); //PLL DISENABLE
Delay_ms(10);
MIPI2DP_Write(0x5A, 1, 0x05);
MIPI2DP_Write(0x93, 1, 0x24); //2 DP lanes no SSC
MIPI2DP_Write(0x95, 1, 0x00); //POST-Cursor2 0dB
MIPI2DP_Write(0x96, 1, 0x0A); //Semi-Auto TRAIN
DP_Read();
buf[0] = (edp.xdot>>1) & 0xFF;
buf[1] = (edp.xdot>>9) & 0xFF;
MIPI2DP_Writes(0x20, 2, buf); //CHA_ACTIVE_LINE_LENGTH
MIPI2DP_Writes(0x22, 2, buf); //CHB_ACTIVE_LINE_LENGTH
}
else
{
MIPI2DP_Write(0x0A, 1, 0x06); //REFCLK 27MHz
MIPI2DP_Write(0x10, 1, 0x26); //Single 4 DSI lanes
MIPI2DP_Write(0x12, 1, 0x59); //DSIA CLK FREQ 445MHz
MIPI2DP_Write(0x13, 1, 0x59); //DSIB CLK FREQ 445MHz
MIPI2DP_Write(0x94, 1, 0x80); //HBR (2.7Gbps)
MIPI2DP_Write(0x0D, 1, 0x01); //PLL DISENABLE
Delay_ms(10);
MIPI2DP_Write(0x5A, 1, 0x05);
MIPI2DP_Write(0x93, 1, 0x24); //2 DP lanes no SSC
MIPI2DP_Write(0x95, 1, 0x00); //POST-Cursor2 0dB
MIPI2DP_Write(0x96, 1, 0x0A); //Semi-Auto TRAIN
DP_Read();
buf[0] = edp.xdot & 0xFF;
buf[1] = (edp.xdot>>8) & 0xFF;
MIPI2DP_Writes(0x20, 2, buf); //CHA_ACTIVE_LINE_LENGTH
MIPI2DP_Write(0x22, 2, 0x00, 0x00); //CHB_ACTIVE_LINE_LENGTH
}
buf[0] = edp.ydot & 0xFF;
buf[1] = (edp.ydot>>8) & 0xFF;
MIPI2DP_Writes(0x24, 2, buf); //CHA_VERTICAL_DISPLAY_SIZE
buf[0] = edp.hsync & 0xFF;
buf[1] = (edp.hsync>>8) & 0x7F;
if(edp.h_pos) buf[1] &= 0x80;
MIPI2DP_Writes(0x2C, 2, buf); //CHA_HSYNC_PULSE_WIDTH
buf[0] = edp.vsync & 0xFF;
buf[1] = (edp.vsync>>8) & 0x7F;
if(edp.v_pos) buf[1] &= 0x80;
MIPI2DP_Writes(0x30, 2, buf); //CHA_VSYNC_PULSE_WIDTH
MIPI2DP_Write(0x34, 1, edp.hbp); //CHA_HORIZONTAL_BACK_PORCH
MIPI2DP_Write(0x36, 1, edp.vbp); //CHA_VERTICAL_BACK_PORCH
MIPI2DP_Write(0x38, 1, edp.hfp); //CHA_HORIZONTAL_FRONT_PORCH
MIPI2DP_Write(0x3A, 1, edp.vfp); //CHA_VERTICAL_FRONT_PORCH
MIPI2DP_Write(0x5B, 1, 0x00); //DP 24bpp
MIPI2DP_Write(0x5C, 1, 0x00); //HPD DISENABLE
MIPI2DP_Write(0x3C, 1, 0x00); //COLOR BAR disabled
DPCD_Write(0x00100, 1, 0x0A);
Delay_ms(20);
MIPI2DP_Write(0x5A, 1, 0x0D); //Enhanced Framing, ASSR, Vstream
Delay_ms(10);
EDID_Read();
EDID_Print();
Timing_Print();
DPCD_Print();
DPCD_Print_Info();
}
Best Regards.